Translating virtual memory in x86 with PAE - memory

Why does translation from a virtual memory address to a physical address with three-level paging (2-9-9-12, 4K page) require multiplying each page index by 8 before calculating the next one?
For example, if I have the virtual address: 0xabde203 (in binary: 1010 1011 1101 1110 0010 0000 0011).
The first step would be to extract "Page directory pointer table" index, which is represented by the two bits - 10, multiply it by 8 => 10000 and summing its value with the external table physical address in order to find the page directory index.
In a normal x86 virtual translation I understand that the paging is done with two level paging (10-10-12), thus multiplying each index (represented by 10 bits) by 4 (2 bits) would equal to the page size.
But why is multiplication done by 8 when using PAE, how is that representing the page directory table?

In traditional 32-bit paging each page directory entry and each page table entry is 4 bytes, so the index is multiplied by 4. In PAE and 64-bit paging, each table entry is 8 bytes, so the index is multiplied by 8.
1024 4-byte entries fit in a 4 KB page, so in two-level paging, each index is 10 bits. 512 8-byte entries fit in a 4 KB page, so in PAE, each index is 9 bits.
Your observation that 4*2^10 is 4K is apt. 8*2^9 is also 4K.

Related

Calculate the number of entries in a Page Table

We have a system that uses 3-level hierarchical page table. Logical address is 32 bit.
We know that the same amount of bits is allocated for each level in the logical address.
The system is byte-addressable.
Physical address is 27 bits, and we have 8192 frames is the physical memory.
I want to calculate the number of entries in each level of the page table.
We have 8192 frames, that is 2^13, so we need 13 bits to represent the frame number.
So 27-13=14 bits for the offset.
That gives us 32-14=18 bits for page number.
We know that we can split it equally, so 6 bits represents each level of the hierarchical page table.
But how many entries are in each level? 2^6? If so - why is that?
Thanks!

What is the size of a page table entry in a multi level page table?

I understand why a multi-level page table saves memory. In the classic 32-bit example, the size of each Page Table Entry (PTE) in a single-level table is 32 bit (4 Bytes). The fact that 20 of the 32 bits are used for page number means there are 2^20 (~1M) possible entries in this table. The total size of a single-level table is therefore 4 Bytes * 1M = 4MB.A two-level page table requires less memory because it does not need all of the second-level pages at the same time.
However, in a lot of examples for the calculations of two-level page table on the internet, people still use 4 Bytes to indicate the size of each PTE. Since we are only accessing 10 of the 32 bits at the first level, shouldn't the size of these PTEs be smaller than 4 Bytes?
The virtual address is broken to 10-10-12 first 10 bits are an index in the first level page table, there, you will find the address of the second level page table, which you index with the seconds 10 bits to find the start of the physical frame which you index with the remaining 12 bits.
Actually each entry contains the number of the virtual page (there are 2^20 such pages) and 12 flag bits.

How to determine the size of the address space of a process?

I'm studying for an operating systems final and the study guide has the following problem:
Problem 1
In a 32-bit machine we subdivide the virtual address into 4 segments as follows:
| 10-bit | 8-bit | 6-bit | 8 bit |
We use a 3-level page table, such that the first 10-bit are for the first level and so on.
What is the page size in such a system?
What is the size of a page table for a process that has 256K of memory starting at address 0?
What is the size of a page table for a process that has a code segment of 48K starting at address 0x1000000, a data segment of 600K starting at address
0x80000000 and a stack segment of 64K starting at address 0xf0000000 and
growing upward (like in the PA-RISC of HP)
And there is an answer provided here:
Solution:
The page field is 8-bit wide, then the page size is 256 bytes.
Using the subdivision above, the first level page table points to 1024 2nd level page tables, each pointing to 256 3rd page tables, each containing 64 pages. The program's address space consists of 1024 pages, thus we need we need 16 third-level page tables. Therefore we need 16 entries in a 2nd level page table, and one entry in the first level page table. Therefore the size is: 1024 entries for the first table, 256 entries for the 2nd level page table, and 16 3rd level page table containing 64 entries each. Assuming 2 bytes per entry, the space required is 1024 * 2 + 256 * 2 (one second-level paget table) + 16 * 64 * 2 (16 thirdlevel page tables) = 4608 bytes.
First, the stack, data and code segments are at addresses that require having 3 page tables entries active in the first level page table. For 64K, you need 256 pages, or 4 third-level page tables. For 600K, you need 2400 pages, or 38 thirdlevel page tables and for 48K you need 192 pages or 3 third-level page tables. Assuming 2 bytes per entry, the space required is 1024 * 2 + 256 * 3 * 2 (3 second-level page tables) + 64 * (38+4+3)* 2 (38 third-level page tables for data segment, 4 for stack and 3 for code segment) = 9344 bytes.
(sic)
My first issue here is in the solution for part 2, where it states that the program's address space consists of 1024 pages. I have no idea how that is being determined, and attempts to work it out or find answers so far have proved fruitless. Is there some equation that would give me that or am I missing something?
I've tried working it out myself but best I can do is evaluate that 256 KB is 2^18 bytes, but I don't understand the relationship between the program's memory use and the number of pages that will be in its address space.
It would also be helpful if someone could explain how I determine the size of a page entry from the given information, or is that just something that if not given has to be assumed to be some value like they do here?
What is the size of a page table for a process that has 256K of memory starting at address 0?
We found in the solution of part 1) that the size of a page is 256 bytes. Therefore, the number of pages for a process consuming 256K of memory is 256K/256 = 1K = 2^10 = 1024

Calculating sizes of page table parameters

I am given a system with 64-bit virtual address space. with page size of 2KB.
Also it is given that the physical memory is of the size 16GB.
I need to calculate the following parameters:
number of page entries (number of lines in the page table), how many bits are needed for the page offset, how many bits are needed for the virtual page number (VPN), and how many bits are needed for the physical page number (PPN).
So, first I concluded that the size of the virtual memory is 2^64 bytes, and that means there are 2^53 entries in the page table.
From the size of a page I concluded that 11 bits are needed for the page offset.
From here I'm not so sure.
Since each virtual address is of the size 64 it, then the VPN is of the size 64 - 11 = 53 bits.
Since the physical memory is of the size 2^34 bytes, then a physical address if of 34 bits. Which means the PPN is of the size 34 - 11 = 23 bits.
Are my calculations correct? and also is my thinking correct?
Help would be appreciated
Some of your results are correct. PPN is 23 bits, VPN is 53 bits.
But all the stuff concerning the page tables is wrong.
A page table contains a set of physical page adresses. Hence as a PPN is 23 bits, one needs 4 bytes (the power of 2 above 23) to describe a PP. If pages are 2k bytes, you can store 2^9 PP adresses par page.
As VPN are 53bits, and each table can resolve 9 bits, the translation can be done by 6 consecutive tables.
If you are not familiar with multilevel pages, there are many good tuturials. See for instance https://en.wikipedia.org/wiki/Page_table
What is certain is that the PT size is NOT 2^53!! First because 2^55 is an insane amount of memory (~10^16). And second, because the total number of PP is 2^23, so why use a table 1 billion times larger... (and this is why we use multilevel page tables)

Calculating maximum physical memory

I have been given the format for page table entries:
Bit 23: Valid Bit
Bit 22: Modify Bit
Bits 22-18: LRU Bits
Bits 17-0: Frame Number
Im told that the system uses 32-bit virtual addresses and pages that are 8192 bytes in size.
How could I calculate the maximum amount of physical memory the system can contain?
So you have 18 bits for page numbers. How many possible numbers (and therefore pages) can be represented by 18 bits?
From the above you'll find how many pages there can be. Then each page has 8192 bytes. How many bytes are there in all possible pages?

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