Port Map-ing to ground in VHDL - mapping

Question

I am new to VHDL and having an issue trying to port map to ground.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity msPC4 is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
a : out STD_LOGIC_VECTOR (3 downto 0);
co : out STD_LOGIC);
end msPC4;
architecture Structure of msPC4 is
component msdff4
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component msFA4bit
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
ci : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
co : out STD_LOGIC);
end component;
component ms21mux4
Port ( d1 : in STD_LOGIC_VECTOR (3 downto 0);
d0 : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal w0, w1, w2, w3: STD_LOGIC_VECTOR (3 downto 0);
signal w4 : STD_LOGIC;
w4 <= '0';
w3 <= '0000';
begin
gmsPC4g1: msdff4 port map (w1,clk,w2);
gmsPC4g2: msFA4bit port map (w2,b,w4,w0,co);
gmsPC4g3: ms21mux4 port map (w0,w3,clk,w1);
a <= w2;
end Structure;
So if you'll notice, I have 3 components, a couple signals to connect everything and such.
What I REALLY want, is for signals w3 and w4 to be SET to ground (tied to logic low, as it were), but for whatever reason, I cannot for the life of me figure out how I am supposed to do this.
FWIW I'm an EE so I'm more accustomed to seeing this from the hardware end. Also, this project specifically has to be done with port maps and not the behavioral stuff. Sorry about that.
Edit: The error is being thrown at lines where w3 is set to '0', w4 is set to '0000'. Double quotes do not fix this error. Moving it inside begin does not fix the error. Inside the begin set I get an "UNEXPECTED TICK" and outside the begin set I get a "UNEXPECTED IDENTIFIER". It just really doesn't want to let me decide the value of something.

Answer 1

Changing your code:
-- w4 <= '0';
-- w3 <= '0000';
begin
w4 <= '0';
w3 <= "0000";
Allows successful analysis, noting there are no other drivers from w4 or w3.
Alternatively you can provide default values in the declarations:
signal w0, w1, w2: STD_LOGIC_VECTOR (3 downto 0);
signal w3: STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal w4 : STD_LOGIC := '0';
-- w4 <= '0';
-- w3 <= '0000';
This also analyzes.
The default value represents the value of a signal prior to a signal assignment.
You can also supply values directly:
gmsPC4g1: msdff4 port map (w1,clk,w2);
gmsPC4g2: msFA4bit port map (w2,b,'0',w0,co); -- w4
gmsPC4g3: ms21mux4 port map (w0,"0000",clk,w1); -- w3
This analyzes.
Or provide constant values:
signal w0, w1, w2: STD_LOGIC_VECTOR (3 downto 0);
constant w3: std_logic_vector(3 downto 0) := "0000";
constant w4 : STD_LOGIC := '0';
-- w4 <= '0';
-- w3 <= '0000';
begin
gmsPC4g1: msdff4 port map (w1,clk,w2);
gmsPC4g2: msFA4bit port map (w2,b,w4,w0,co);
gmsPC4g3: ms21mux4 port map (w0,w3,clk,w1);
which also analyzes.
Notice the double quotes used in string literal values ("0000"). Single quotation marks (ticks) are used for character literals with graphical representation.
You are not using either package std_logic_arith nor std_logic_unisigned. Their use clauses are superfluous.