I'm reading about virtual memory and I have some doubts reguarding multi-level paging.
I saw that in a N-level page table, the N-1 tables are used to store indexes to the next level tables.
This is my point:
Assuming the case of RISC-V Sv39 (Section 4.4 of RISC-V privileged architecture). We have the physical address of 1-level page root in SATP.ppn.
Virtual address is composed as follows:
<38-29> VPN[2] (9 bits)
<28-21> VPN[1] (9 bits)
<20-12> VPN[0] (9 bits)
<11-0> offset (12 bits)
After a TLB-miss, a page walk starts:
index_to_second_level_PT = SATP.PPN + VPN[2]
index_to_third_level_PT = index_to_second_level_PT + VPN[1]
physical_address = index_to_third_level + VPN[0]
My questions is:
Do all the idexes in the PTE (i.e, computed in step 1., 2., and 3.) are physical addresses? this makes sense to me, since once we get the physical address of the next table we can retrieve it from physical memory.
Moreover, always in RISC-V manual, also physical addresses and PTE entries are formatted with multiple fields (PPN[0], PPN[1], and PPN[2]). I understand that the virtual address is partitioned into three 9-bit fields to index the multi-level page table, but I don't understand why also the physical address is partitioned in such way.
Thanks in advance to anyone who responds.
Related
If virtual memory has a 32-bit address are there 2^32 entries or is the size of total entries 2^32 bytes? or both?
The reason I ask is because I thought it only meant 2^32 entires.
After doing the following problem I am not sure:
Suppose a machine has 48-bit virtual addresses and 32-bit physical addresses.If pages are 4KiB, how many entries are in the page table if it has only a single level?
Solution: 2^48/2^32 = 2^16 pages.
However, number of entries/size of page != number of pages.
size of total entries/size of page = number of pages.
So, I'm wondering if a 32-bit address means there are 2^32 entries or if total entries equal 2^32 bytes or both.
Jinan, i think you are confused in linux memory related stuff.
your question for :
If virtual memory has a 32-bit address are there 2^32 entries or is the size of total entries 2^32 bytes? or both?
Page table entries are not depend only virtual address space, page size and physical memory are also need to calculate the entries.
I'm taking your example:-
Suppose a machine has 48-bit virtual addresses and 32-bit physical addresses.If pages are 4KiB, how many entries are in the page table if it has only a single level?
Number of entries in page table will be = 2^36.
A page entry is used to get address of physical memory. Here we assume that single level of Paging is happening. So the resulting page table will contain entries for all the pages of the Virtual address space.
Number of entries in page table =
(virtual address space size)/(page size)
Virtual address = 48 Bit
Page size is = 12 bit ((2^12) is equal to 4KB).
Using above formula we can say that there will be 2^(48-12) = 2^36 entries in page table.
Size of Page Table
No. of bits required to address the 32bit Physical memory = 32.
So there will be 2^(32-12) = 2^20 page frames in the physical memory. And page table needs to store the address of all these 2^20 page frames. Therefore, each page table entry will contain 32 bits address of the page frame..
Since memory is byte addressable. So we take that each page table entry is 32 bits i.e. 4 bytes long.
Size of page table =
(total number of page table entries) *(size of a page table entry)
= (2^36 *4) = 256GB
Excluding the valid, dirty and reference bits, considering only actual "mapping" from virtual address space to physical address space, why is it said that the size of a page table entry is determined by the number of bits required to reference a page from the main memory (Like here: https://stackoverflow.com/a/14770650/3684931)
My argument is that since a physical address can be in secondary storage too (which is the point of using virtual memory), the size of a page table entry should simply be equal to the number of bits to required to reference any page among all the pages in the virtual memory.
To give an example, if virtual address space is addressable by 64 bits, main memory is addressable by 48 bits and page size is 16KB (addressable by 14 bits), a page table should map (64 - 14) 50 bit addresses to (64 - 14) 50 bit addresses and not (48 - 14) 34 bit addresses.
It could map to 34 bit addresses if the page exists in main memory, but otherwise, the upperbound should be 50 bits which should be considered while calculating the size of a page table.
Am I missing something here?
Page table entries are sized to support the virtual address size and the maximum amount of physical memory supported. They are not sized based on any aspect of the secondary storage.
In your example, the page table has to support mapping 2^50 virtual pages to a possible 2^34 physical pages. Thus a page table entry will use 34 bits to hold the physical page number.
If a page is not present in memory, and it was previously paged out to secondary storage, then a data structure (like a hash table) can be used to locate where in the paging file the page is located. You don't need to use the page table structure to do this.
The size of a page table must account for:
1. Control bits
2. Access restriction bits
3. The page size
4. The number of bits requires to access the required number of pages.
The page table entries correspond to the virtual memory. The number of entries times the page size is the virtual address size.
The entries themselves only need to address physical memory.
As the title already says, I want to know what the range of the physical addresses of the associated segment is, if the CS register of a 8086 has the value 0xA000?
Shift left 4 bits.
0xa0000 + whatever value is hqving CS applied.
Since the cpu registers and other values are 16-bit, you get 0xAxxxx where xxxx is a 16 bit value. That is, the segment register specifies which 64k can be addressed. By windowing like that, you can get a 20-bit physical addresss space.
See this old post for more info. Once upon a time that was common teaching, but I suppose now it's harder to find. Maybe you can find some old books via Amazon Marketplace.
After a little research I found that this is the correct answer to the question:
0xA0000 + 0xFFFF = 0xAFFFF (highest physical address of the segment)
0xA0000 + 0x0000 = 0xA0000 (lowest physical address of the segment)
So the range of the physical addresses is 0xA0000 - 0xAFFFF.
A certain computer provides its users with a virtual memory space of 2^24 words. Computer has 2^18 words of physical memory. The virtual memory is implemented by paging, and the page size is 256 words. A user program generates the virtual address 24A72E (HEX). Explain how the system established the corresponding physical location...
Logical Page (i.e. the page table entry) = 24a72Ex / 256
That provides a index to a page table entry. That page table entry identifies the physical memory page.
The word offset into the page is is 24a72Ex MOD 256
I have been given the format for page table entries:
Bit 23: Valid Bit
Bit 22: Modify Bit
Bits 22-18: LRU Bits
Bits 17-0: Frame Number
Im told that the system uses 32-bit virtual addresses and pages that are 8192 bytes in size.
What would be the total size in bytes of the page map table?
If an inverted page map table is used what would be its total size in bytes if the LRU field within each PTE is reduced to 3 bits?
I have been helped with this problem, and calculated that the maximum physical memory of the system is 2GB. I'm not sure if I need to take the 32 bit virtual address data given into consideration when calculating the total size of the page map table.
Looks like there isn't enough information to answer this question.
See, the page table size is equal to the number of entries in it times the size of each entry.
First, I don't know if the page table entries are 24-bit-long or 32-bit-long or bigger. That's not explicitly specified.
Second, if there's only one page table involved in translation of virtual addresses into physical addresses, a page table has to cover the entire 32 bits of the virtual address. Since a single PTE only handles 13 (because the page size is 2^13=8192 bytes), you'd need 2^(32-13)=2^19 entries in this case.
Now, if there's a hierarchy of page tables involved in the translation, in other words, the entries of the first page table (often called page directory) point to a second-level page table and those either point to the code/data pages or to a third-level page table and so on, you get the idea... in this case the answer is going to be different. But it's not specified whether there's just one page table or a chain of multiple page tables.
In my opinion, a page table of 2^19 entries is unlikely. A page table is usually the size of a single page (sometimes smaller). So, if, for example, PTEs are 32-bit, you have 8192/4=2048 PTEs in a PT and that covers only 11 (2^11=2048) out of the remaining 32-13=19 bits of the virtual address. The other 19-11=8 bits of the virtual address must be taken care of by another page table, page directory, having only 2^8=256 entries, provided the entries are the same in the page table and page directory.
Given the provided information, there's no definitive answer here, only guesses.