vitis hls 2020.2 Pre-synthesis failed, but it didn't prompt any errors. How can I find out the cause of the error and fix it？ - xilinx

Question

#define READ_COL 4
void read_data(kern_colmeta *colmeta
, int ncols
, HeapTupleHeaderData *htup
, cl_char tup_dclass[READ_COL]
, cl_long tup_values[READ_COL])
{
char *addr ;//__attribute__((unused));
EXTRACT_HEAP_TUPLE_BEGIN(addr, colmeta, ncols, htup);
EXTRACT_HEAP_TUPLE_NEXT(addr);
EXTRACT_HEAP_TUPLE_NEXT(addr);
EXTRACT_HEAP_READ_32BIT(addr, tup_dclass[3],tup_values[3]);
EXTRACT_HEAP_TUPLE_NEXT(addr);
EXTRACT_HEAP_TUPLE_NEXT(addr);
EXTRACT_HEAP_TUPLE_NEXT(addr);
//EXTRACT_HEAP_READ_POINTER(addr,tup_dclass[1],tup_values[1]);
EXTRACT_HEAP_TUPLE_NEXT(addr);
//EXTRACT_HEAP_READ_POINTER(addr ,tup_dclass[2],tup_values[2]);
EXTRACT_HEAP_TUPLE_END();
}
void accel (char *a, char *b)//, int* o)
{
#pragma HLS INTERFACE m_axi depth=125 port=a
#pragma HLS INTERFACE m_axi depth=1984 port=b
kern_colmeta col[16];
memcpy(col, b, sizeof(kern_colmeta)*16);
HeapTupleHeaderData *htup;
htup = (HeapTupleHeaderData *)a;
cl_char tup_dclass[READ_COL];
cl_long tup_values[READ_COL];
read_data(col, 16, htup, tup_dclass, tup_values);
}
The top function is accel(), error occurs in the code when calling EXTRACT_HEAP_READ_32BIT(). C simulation results are normal，but as once try to run synthesis, it faild. error log just like as follows:
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 205.967 MB.
INFO: [HLS 200-10] Analyzing design file '/root/gyf/hls/Unable_to_Schedule/kernel_fun.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.23 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.21 seconds; current allocated memory: 207.566 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vitis' flow target.
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 3.3 seconds. CPU system time: 0.35 seconds. Elapsed time: 3.56 seconds; current allocated memory: 209.139 MB.
Pre-synthesis failed.
while executing
"source accel.tcl"
("uplevel" body line 1)
invoked from within
"uplevel \#0 [list source $arg] "
INFO: [HLS 200-112] Total CPU user time: 5.81 seconds. Total CPU system time: 0.99 seconds. Total elapsed time: 5.43 seconds; peak allocated memory: 208.758 MB.
INFO: [Common 17-206] Exiting vitis_hls at Fri Feb 25 13:28:33 2022..
The Project code

Answer 1

I have exactly the same error:
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 45.76 seconds. CPU system time: 0.94 seconds. Elapsed time: 46.21 seconds; current allocated memory: 194.761 MB.
Pre-synthesis failed.
while executing
"source ../scripts/ip_v6.tcl"
("uplevel" body line 1)
invoked from within
"uplevel \#0 [list source $arg] "
I would be interested to know how I can track the error source. I also have the same error message if I launch viti_hls GUI.