Task to measure clock frequency in System Verilog (pass clock signal by reference) - task

Question

I'm new to SV for verification and as a first attempt to a object oriented testbench, I'm trying to verify a simple clock generator design.
I would like to constantly monitor the multple clock outputs of the macro, given a certain configuration and clock input. To do so I need to be able to measure the frequency of multiple clock signals.
Ideally, I thought of something like this for my checker class:
get trigger and retrieve configuration details
start a freq_meter task for each output clock I need to measure
Each freq_meter task would do the following:
receive a clk signal from the virtual interface
start time measure
count N clock posedges
return the evaluated frequency
class checker_monitor;
virtual clkgen_if clkgen_vif;
task run();
// launch freq measure
fork
freq_meter(clkgen_vif.clk_out_1);
freq_meter(clkgen_vif.clk_out_2);
freq_meter(clkgen_vif.clk_out_3);
join
// check that returned frequencies are correct
endtask
task freq_meter(input logic clk, output logic freq);
time_start = $time;
repeat(N+1) # (posedge clk);
time_end = $time;
period = (time_end - time_start)/N;
freq = 1/period;
endtask : freq_meter
Any suggestions on such a problem? I'm stuck now at passing a clock signal by reference to the task from the virtual interface.
Best,
abet

Answer 1

Change the input parameter of the task to the reference parameter like in following snippet.
task freq_meter(ref logic clk, output int freq);
Note: As was pointed out in the comments this will work only when clkgen_vif.clk_out_N are variables not nets. My assumption is that they are defined as logic in the clkgen_if interface.
EDIT: I've created a working example on EDAPlayground(link). I also changed the output parameter to int instead of logic as frequency measurement would return only 0 or 1.