I cannot see the contents of a memory - memory

Question

I have a problem when I try to simulate a circuit which is supposed to process data taken from an SRAM memory. Firstly, an SRAM memory is filled with data, this could be seen if one has a look over the last testbench, than, the stored data will be processed by an automaton. Then, the output, in some specific situations, is stored in another SRAM memory. Thus, when simulated, the circuit behaves in a strange way, because the rd_data_instrucions, which represents read data from the first SRAM memory, is always undefined. Consequently, all other signals depending on rd_data_instructions are undefined too. The code is posted here.
P.S.: Modules sram_1port_instructions and sram_1port_data should behave as clocked SRAMs, having a write enable signal so that when wr_en is high, the memory stores data received(wr_data) and when wr_en is low, the memory could output data (rd_data).
Module user represents an "interface" which facilitates the writing process so that writing in the SRAM instruction memory does not require the address to which data is stored because this module provides a mechanism which increments the "write-address-pointer" of the memory. Further, we can see the corresponding testbench for this module. Then, we can see the corresponding module of another memory, which is created for output storage, and a module designed to facilitate the reading process (i.e. something similar to the previous situation, but, instead of facilitating the writing process, it eases reading).
Last, but not least, we may distinguish a wishbone module, which is supposed to interconnect all the previous modules in order to create a digital system. Consequently, an automaton takes data from the SRAM instruction memory, then outputs some data which is stored in another memory. Finally, the outcome could be read from the SRAM data memory.
The problem occurs when I try to simulate the system because I encounter difficulties when trying to read some signals, e.g. rd_data_instructions, which should display the previously stored values from the SRAM instruction memory, implicitly the "in" signal, which should provide the input for the automaton, and so on. Within the wishbone module, I used a special signal labelled "start" which sets the write-enable on 0 so that the SRAM memory is prepared for the reading process. This special signal actually triggers the automaton, by "feeding" it with input data from the memory.
//wishbone module
module wishbone(
input clk,rst,start,
output reg [2:0]in,
output reg wr_en_instructions,wr_en_display,
input [2:0] wr_data_instructions,//created for usr, in order to make possible to write data
output reg [3:0] wr_data_display,
output [2:0] rd_data_instructions,
output [3:0] rd_data_display,//created for user, in order to make possible the display
output [12:0]o
);
reg [15:0] pointer_instructions,pointer_display;
initial wr_en_instructions = 1'b1;
control_unit i0(.clk(clk),.rst(rst),.in(in),.o(o));
user i1(.clk(clk),.wr_en(wr_en),.address_in(pointer_instructions),.wr_data(wr_data_instructions),.rd_data(rd_data_instructions));
display i2(.clk(clk),.wr_en(wr_en_display),.address_in(pointer_display),.wr_data(wr_data_display),.rd_data(rd_data_display));
integer i = 0;
always # * begin
wr_en_display = ~wr_en_instructions;
end
always #(posedge clk) begin
if(start) begin
pointer_instructions <= 16'b0;
pointer_display <= 16'b0;
wr_en_instructions <= 1'b0;
end
else begin
$display(rd_data_instructions);
if(!wr_en_instructions) begin
if(rd_data_instructions == 3'b1xx) begin
wr_en_instructions <= 1'b1;//???
end
else if(rd_data_instructions == 3'b010) begin
in <= rd_data_instructions;
wr_data_display <= o;
pointer_instructions <= pointer_instructions + 1;
pointer_display <= pointer_display + 1;
end
else begin
in <= rd_data_instructions;
pointer_instructions <= pointer_instructions + 1;
end
end
else begin
i = i + 1;
end
end
end
endmodule
//testbench for top module
module wishbone_tb(
output reg clk,rst,start,
output [2:0]in,
output wr_en_instructions,wr_en_display,
output reg [2:0] wr_data_instructions,//created for usr, in order to make possible to write data
output [3:0] wr_data_display,
output [2:0] rd_data_instructions,
output [3:0] rd_data_display,//created for user, in order to make possible the display
output [12:0]o
);
wishbone cut(
.clk(clk),.rst(rst),.start(start),
.in(in),
.wr_en_instructions(wr_en_instructions),.wr_en_display(wr_en_display),
.wr_data_instructions(wr_data_instructions),
.wr_data_display(wr_data_display),
.rd_data_instructions(rd_data_instructions),
.rd_data_display(rd_data_display),
.o(o)
);
initial $dumpvars(0,wishbone_tb);
initial begin
clk = 1'd1;
repeat (600000)
#100 clk = ~clk;
end
initial begin
rst = 1'b1;
#400 rst = 1'b0;
end
initial begin
start = 1'b0;
#13000400 start = 1'b1;
#400 start = 1'b0;
end
initial begin
wr_data_instructions = 3'd1;
#3000400 wr_data_instructions = 3'd2;
#1000000 wr_data_instructions = 3'd1;
#3000000 wr_data_instructions = 3'd0;
#2000000 wr_data_instructions = 3'd3;
#1000000 wr_data_instructions = 3'd1;
#3000000 wr_data_instructions = 3'd4;//halt
end
endmodule