2-way set associative cache hit/miss ratio calculations - memory

Question

I am having a hard time figuring out how to know when there will be a hit or a miss. Here is the problem I'm doing (I have the answer but I can't figure out how they got the answer):
A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each.
Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. (I understand this and have done work and gotten the answer)
Compute the hit ratio for a program that loops 3 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Here is the answer:
First iteration of the loop: Address 8 is a miss, and then entire
block brought into Set 1. Hence, 9-15 are then hits. 16 is a miss,
entire block brought into Set 2, 17- 23 are hits. 24 is a miss, entire
block brought into Set 3, 25-31 are hits. 32 is a miss, entire block
brought into Set 0, 33-39 are then hits. 40 is a miss, entire block
brought into Set 1 (note we do NOT have to throw out the block with
address 8 as this is 2-way set associative), 41-47 are hits. 48 is a
miss, entire block brought into Set 2, 49-51 are hits.
For the first iteration of the loop, we have 6 misses, and 5*7 + 3
hits, or 38 hits. On the remaining iterations, we have 5*8+4 hits, or
44 hits each, for 88 more hits.
Therefore, we have 6 misses and 126 hits, for a hit ratio of 126/132,
or 95.45%.
I still having problem wrapping my head around how do I figure out what memory addresses/blocks will be hits or misses.

Answer 1

There are some ambiguities in the question:
Cache line size is not given
Each memory entry is said to be 8 words long.
Therefore I've made few assumptions:
Cache line is 8 words
Main memory is word addressed
The main memory has 2048 entries, hence 11 bits for the memory address. Cache line is 8 words wide, hence the least 3 bits are used for the word selection within a cache line. There are 4 cache blocks, hence the next two bits are used for the indexing. This leaves 6 bits for the TAG.
When the address 8 (x00000001000) is issued, index is 01, and the TAG is 000000.
This is not in the cache, hence a miss.
For address 9 (x00000001001), index is 01, and the TAG is 000000. This is already in the cache, hence its a hit.
For address 10 (x00000001010), index is 01, and the TAG is 000000. This is already in the cache, hence its a hit.
The same pattern continues until address 15 (x00000001111).
When the address 16 (x00000010000) is issued, index is 10, and the TAG is 000000.
This is not in the cache, hence a miss.
When the address 17 (x00000010001) is issued, index is 10, and the TAG is 000000. This is already in the cache, hence its a hit.
The same pattern continues until address 23 (x00000010111)
8-15 :cache index 01, TAG 00000: 1 Miss, 7 Hits
16-23 :cache index 10, TAG 00000: 1 Miss, 7 Hits
24-31 :cache index 11, TAG 00000: 1 Miss, 7 Hits
32-39 :cache index 00, TAG 00000: 1 Miss, 7 Hits
Now for address 40 (x00000110000), index is 10, but the TAG is 000001. This a miss, when the data is brought from memory, this can go to the second entry in the cache block indexed by 10, as our caches are 2 way.
40-47 :cache index 01, TAG 00001: 1 Miss, 7 Hits
48-51 :cache index 10, TAG 00001: 1 Miss, 3 Hits
For the first iteration: 6 misses and 38 hits. For the second iteration, 44 hits and for the third iteration 44 hits.
So overall we have 126 hits over 142 accesses.
The hit ratio is 126/132