In the case that a virtual memory address has a length of 40 bits, the physical memory address has a length of 28 bits, how can we find the size of the physical and virtual memories?
All you have to do is raise two to the number of bits of the memory address.
The virtual memory size is bytes.
The physical memory size is bytes.
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My understanding of word size and memory addresses is as follows. An 8bit machine will have an address bus of size 8bit and have 256 memory addresses. A memory address is the location of each address so this machine can make use of 256 bytes of RAM. Now a 32 bit machine has an 32 bit word size ie 4bytes. At this point I get confused. In terms of usable memory, online tells me 4gb but if each memory address is 4bytes in size then surely it only has 1 million total memory addresses available ie 1gb of ram can be used? What am I mixing up here?
This question already has answers here:
Size of a Word and addressing
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How does 32-bit address 4GB if 2³² bits = 4 Billion bits not Bytes?
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Closed 2 years ago.
I have a question regarding (RAM) memory units:
for a cpu architecture x32,
we will have 32bit size cpu registers, as well as data bus to ram of 32 wire and address bus of 32 wire.
so the maximum memory address unit is 2^32 = 4,294,967,296
on other words we have 4,294,967,296 memory units, and for each memory unit, data bus (32) size should be writable so for each memory unit its size should be 32bit to handle the data bus
if i concluded right which i doubt, (Ram) total memory size should be = no of memory units * size each =
4,294,967,296 * 32 = 137,438,953,472 bit. which is not true
after research, i found out, rams unit memory are standardized to be 8 bit per each memory unit,
so if this is the case, how come single memory unit (8bit) can store (32bit data bus) ?
Indeed what is true, is that if you won't have 32 bit data, what this tells you is that the memory can hold 2^32 addresses for memory. However for each memory what you have is a byte, or eight bits, then you will have about 4 GiB = 4*2^30 Bytes = 2^32 bits.
I am trying to calculate the maximum memory size knowing the bit length of an address and the size of the memory cell.
It is my understanding that if the address is n bits then there are 2^n memory locations. But then to calculate the actual memory size of the machine, you would need to multiply the number of addresses by the size of the memory cell. Is that correct?
To put it another way,
Step 1: calculate the length of the address in bits (n bits)
Step 2: calculate the number of memory locations 2^n(bits)
Step 3: take the number of memory locations and multiply it by the Byte size of the memory cells.
If each cell was 2 bytes for example, would I multiply 2^n bits (for address length) by the 2 Bytes per memory cell.
So total memory would be 2^n bits (address size) * x bytes (cell size)?
"actual memory size of the machine"
I will assume here that you mean the physical address space of the machine in question, ignoring virtual addressing, etc.
Most modern machines are byte-addressable (8-bit) meaning that each address refers to 1 byte. In this case, assuming that you have an n-bit processor with a matching n-bit address bus (there are cases where these aren't the same, e.g. Pentium processors) the number of memory locations possible is 2^n bytes.
If you have more specialized hardware, (embedded microcontrollers, etc) that are word addressable (16-bit, 32-bit), then you are correct that you would multiply 2^n * (word-size in bits) / (8) = # of bytes.
That being said, when you take into consideration virtual addressing and physical bus sizes that might not be the same as the processor's address lines, you would have to take a look at that specific machine for the "theoretical limit".
Suppose that I have a computer with an address register of size 16 bits (MAR, for example). The smallest addressable unit in this computer is a word and each word is of size 2 bytes. What is the maximum memory size (in bytes) this system can support?
I thought it would be 2^16 = 65536 bytes, but the part about the smallest addressable unit implies that this is not the way to solve it.
Thanks in advance
There is no direct correlation to the maximum amount of memory a system can support, and the size of address registers.
16bit computers 30 years ago could very well support more than 64 kilobytes. On the other hand, modern 64bit processors typilcally only have lanes for 52 bits (or less), but even so a typical computer cannot nearly support 2^52 bytes of memory.
Typical 64bit computers today could in theory address 16 exibytes, but present-time CPUs only support 4 petabytes of phyisical and 256 terabytes of per-process virtual memory. Typical desktop mainboards support 128GiB maximum, if you buy extra expensive DIMMS. With affordable DIMMS, you're limited to about half as much (there are only so and so many slots).
Operating systems typically allow for main memory sizes in the hundreds of gigabytes only (e.g. 512 GiB for Windows 8 enterprise/professional, and 128GiB otherwise, or as little as 16GiB for Windows 7 Home Premium)
Generally the smallest addressable size is one byte, as you have calculated it, if it were one byte it would be 2^16*1 = 65536 bytes. However, because on this system there are two bytes per address, it is actually 2^16*2 = 131072 bytes.
Does anyone know what aspect ratio mean in memories? and how it's different in block ram and distributed ram in Xilinx FPGA?
Thanks
"Aspect ratio" refers to the number of address bits and data bits when accessing memory.
For example, say you have memory that holds 65,536 bits. If you use 8 data bits per address, you have 8,192 addresses (65,536 / 8 = 8,192), which means 13 address bits (2^13 = 8,192). So one aspect ratio for accessing 65,536 bits is 8 data bits and 13 address bits.
But say you want 16 data bits per address. Then you can only have 4,096 addresses since 4,096 * 16 is 65,536, and that's all the memory you have. In that case, you can only have 12 address bits. So another aspect ratio for accessing 65,536 bits of memory is 16 data bits and 12 address bits.
Aspect Ratio is another term that is used for the data organization of a RAM block.
In Xilinx FPGAs, a Block RAM is a dedicated two-port memory containing several kilobits of RAM. The FPGA contains several (or many) of these blocks.
Inside of each small logic block is a configurable lookup table. It is normally used for logic functions, but you can reconfigure it as a few bits of RAM. You can combine several (or many) of them into a larger RAM. This is distributed RAM.
Both types of RAM can be initialized with data, or used as ROM.
More Information can be found here:
http://www.xilinx.com/support/index.htm#nav=sd-nav-link-182711&tab=tab-sd