How does a computer know that it's an integer, not a memory address or not an ascii?
How does a computer knows it, to interpret it in the right way?
A computer generally doesn't know (unless you have some advanced architecture where each memory location has a tag value indicating what's stored there). All it stores and retrieves are bits.
Programs know how to interpret those bits because they were told by the programmer how to do so. Assuming the programmer was competent of course :-)
The computer really doesn't. It is the program that must "know". Programs, in addition to just storing the data in memory, also store the variable type.
A computer is smart enough to know how to interpret bits. Computer hardware architectures are responsible for interpreting memory endian type (little or big endian) and also the word size (8 bit, 16 bit, 32 bit, 64 bit). Hardware generally can interpret these types of values. It does not really know anything about whether it is an integer, memory address, or ASCII.
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I'm attempting to simulate a 32 bit computer under a very scuffed architecture I have come up with on my own. I am probably doing everything wrong but it's just a fun thing I'm doing to teach myself C.
I am encountering a slight issue where I have no idea how many bytes of a number I should save to memory.
At the moment I have an instruction that looks like this: CODE, (addressing info), add-a, add-b, add-c.
the opcode and addressing info is 4 bits long, and the addresses are 8 bits long. If I add 2 32 bit numbers (b and c) they get saved at address a. The issue arises when I have a number that is less than 32 bits. For example, if I have an array of 1 byte chars and for whatever reason I want to add 1 to one of the numbers, when I save the 1 byte char back to that array, it would be written as a 32 bit number, thus overwriting the 3 subsequent chars.
I'm not really sure the best way to tackle this issue but I have a few ideas.
Idea 1:
Just do everything in 32 bit chunks. Let the programmer deal with the issue themselves. (do some funky bitwise manipulation to fit the 1 byte char back into the array. maybe with a mask)
I don't want to do this as it would make the code messy.
Idea 2:
Only allow addresses every 32 bit . If every number is 32 bits long, then no number will be overwritten.
This sucks as as far I can tell, nothing does this. It would make saving smaller numbers take up 4 times more memory than they need to.
Idea 3:
Stop working with 32 bit numbers. Only ever add, subtract, store, get 8 bit numbers. This would work and probably be less messy but would also be very annoying. Adding 32 bit numbers would suddenly take at least 4 lines of code, the programs would then run slower. It would also mean moving lines of code around would also take at least 4 lines of code as each line of code is 4 bytes long.
Basically I have no idea what I'm doing and I can find anyone online talking about this. I'm sure either there is something glaringly obvious, or I'm doing something stupid and I will need to redesign the whole system...
also side note, I'm not sure if this is the correct place to ask this kind of question but if it isn't I would love to know where is
All the ideas you mention seem to share a common concept, which is to limit what the hardware does and make software make up the rest of its desires/requirements by (a) assembling larger items from smaller storage units, and vice versa, (b) packing smaller items into larger storage units.
Generally speaking this is how computation works anyway, providing only limited capabilities in hardware, and making software make up any shortfall. The limited capabilities, ideally, are well matched to common software patterns, such as for strings, integer of various sizes, floats, etc..
Where the line is drawn between hardware-built-in capabilities and software compensation has been changed many times by many processors over the years.
Software generally has to do both of these with any machine organization existing today. If you want an array of Boolean values, then you would probably want to pack them into bytes (or words) and set/extract bits from them, which is (b). On the other hand if you want long strings or multiword numeric data, then software assembles some larger number of storage units into a whole, which is (a).
Modern 64-bit hardware offers at least 1-byte, 2-byte, 4-byte and 8-byte data (modulo vectors). By offering these data sizes, we mean that it provides for instructions that directly operate on these sizes, i.e. single instructions that do useful things with them.
However, there are no modern bit-addressable machines, so if you want smaller than a byte (quite reasonable sometimes) you have to handle that with software.
Further if you want 3-, 5-, 6-, or 7-byte data, the hardware doesn't necessarily provide that directly — though support for misaligned load helps, since with that you can load a larger size and mask off the bad pieces; stores similar with read-modify-write.
If you want 9-byte or larger, you'll have to use multiple load and store instruction, though again misaligned capabilities in the hardware help with odd sizes.
Some instruction sets have drawn a limited line by removing byte load & store instructions (while remaining byte addressable) though provided dedicated instructions to extract the proper byte from a word in a register so as to still provide some hardware acceleration for byte operations on hardware that doesn't have misaligned loads, since without either byte loads, misaligned capabilities, or special helper instructions, extracting the proper byte from a word can take multiple instructions and/or repetitive loading of the same memory word for sequential access.
I advocate the load/store model. That means rich load & store instructions:, load signed byte, load unsigned byte, signed half, unsigned half, word (32), double. And arithmetic in such a model would be register to register, so then you don't need smaller than word-sized addition. No mainstream programming language demands byte addition, and having byte arithmetic doesn't even offer optimization in a load/store architecture.
However, you will want to take the architecture as a whole into account in designing the individual instructions.
I'm currently working on app that loads blob of tightly packed data which contains different integer types (sized from char to int) that might not be properly aligned.
So, can I use simple *(short*)ptr or similar accesses to that data? Test on my iphone 5 shows no problem with that, but I'm not sure about all cases on all newer processors.
I did find some related informations, like this:
ARMv6 and later, except some microcontroller versions, support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed atomicity.
but in case of words it seems that on 32-bit and 64-bit ARMs word 32 and 64 bit accordingly, which would mean short requires proper alignment on 64-bit machine.
So, can I assume this is safe, or should I use some keywords like __packed?
Or should I rather avoid it completely and recreate my data so it always have proper alignment (or always use memmove when data is from external source and cannot by permanently modified)?
It's ages ago that I tried it. And it worked, but every single access to unaligned memory caused a trap, which took considerable time. I'd suggest you measure how long it takes to add a million aligned shorts vs a million unaligned shorts. If you have a few hundred or thousand unaligned numbers, nothing to worry about.
__packed works reasonably fast. ARM has some clever instructions to do unaligned access with very few instructions. Again, I'd measure how long that takes. My experience with this is not current.
I'm working on a driver for reading smart cards (PC/SC), and I've been reading the data in a forced 8-bit manner, even if the card itself might have a 16-bit chip. I have two questions, one is: how would I tell whether the card conforms to a 16-bit or 8-bit architecture, and the other is: would there be a performance boost to treating the 16-bit system as 16-bit?
Would there be a performance boost to treating the 16-bit system as
16-bit?
No.
The CPU is internally 8, 16 or even 32 bit. But all current processor cards operate over either an ISO 7816-3 (contact) or ISO 14443 (contactless) interface. It's this interface that controls the speed, not the CPU. The CPU uses an outer clock for this, but all the latest smart cards use an internal clock that is running at much higher speeds.
As long as the interfaces are not updated, the "choice" between 8 or 16 bit doesn't matter a bit, let alone 8. I've put "choice" between quotes because I don't see where you have any choice in this.
I have an object that uses more than 2 gigabytes of virtual memory
But Delphi only managers 2 GB
I'm considering ether making a number of objects and grouping them and using the windows wow64 method some how and use 64 bit windows.
Or just upgrading memory manager to 4 GB and build it around Int64.
effectively I need TStream as the base object with Int64 used, instead of integers.
Lexdean, you're saying:
effectively I need TStream as the base object with Int64 used, instead of integers
Well then, you're in luck (twice) because:
Delphi's TStream uses Int64 for position, it can access files much larger then 4Gb.
If a TStream interface is enough, you can write your own TStream to do whatever you want, you don't need to wait for an native 64bit Delphi compiler.
But if I were to answer the question in the title:
How to write a memory manager that maps 4 giggs for Delphi
There's no way to do that with an 32bit compiler. Join the crowd of people asking for an 64 bit Delphi compiler!
Having a single 2 gigabyte object is not a good idea. If memory is fragmented you won't be able to allocate one even if the amount of free memory is enough. I would suggest that you try to use a list of smaller objects.
(I remember how in Turbo Pascal (the predecessor to Delphi) a variable couldn't be larger than 64 kilobyte... Oh, the times... ;)
Unfortunately there's no Delphi compiler as of yet that compiles 64-bit code. You can get more out of your 32-bit address space if you put {$SetPeFlags IMAGE_FILE_LARGE_ADDRESS_AWARE} in the DPR, though. It sets a flag in the PE header that lets Windows know it can allocate more than 2 GB of virtual memory to it.
Guffa's right, though. If your object is trying to grab 2GB+ of contiguous memory, you're probably doing something wrong. What are you trying to do? Maybe there's a simpler way...
You can use AWE APIs to obtain access to more memory in win32 apps. But you have to think your code around AWE rather than adapt AWE usage for your code. What I mean is that you can write a TAWEMemoryStream ... but it is not a good idea.
Why do computers have byte-addressable memory, and not 4-byte-addressable memory (or 8-byte-addressable memory for 64bit)? Yeah, I see how it could be useful sometimes, it just seems inelegant and excessive. Are the advantages substantial, or is it really just because of legacy?
Processors actually do access memory in quantities of 64-bit (x86 did since Pentium or so); 64-bit processors often have a 128-bit bus. Plus, in accessing main memory, you have bursts that fill an entire cache line, which is even larger units of memory.
It's only the addressing that is byte-based; this adds little overhead and is not excessive at all.
Today, you absolutely need byte-based addressing for networking protocols. Implementing TCP with word-based addressing would be difficult: what do you want read() to return if what you received where 17 bytes? Likewise, higher layers are byte-based: HTTP would be fairly difficult to implement if you get a request line like "GET / HTTP/1.0" be presented in units of four bytes. You essentially would have to split the words back into bytes with shift operations and such (which now the processors do in hardware, thanks to byte-based addressing).
Largely historical reasons - it has become the standard that CPUs understand. Here is a good discussion on it:
Generally, a size has to be chosen to
be convenient for both data and
machine instructions. 8 bits (256
values) is enough to accommodate
common characters in English and some
other languages. Designers of 8-bit
processors presumably found that being
able to encode 256 common instructions
as one byte was a "reasonable
tradeoff". And at the time, 8 bits was
also generally enough to encode other
things such as a pixel colour or
screen coordinate. Having a byte size
that is a power of 2 may also have
been felt to be a "neater" design. It
is interesting to note that, for
example, Marxer, E. (1974), Elements
of Data Processing, describes a byte
as being either 6-bit and 8-bit
depending on whether the computer was
of the "octal" or "hexadecimal" type.
Certainly, other sizes were used in the early days.
We needed to settle down on some size for standardization. People chose 8-bit size for the reasons mentioned by Shane above. since then we are stuck with byte addressable memory. now it is impossible to change due to various compatibility issues and the fact that OPCODES are a byte long only. but using a trick, memory is easily made word-addressable to fetch/store data/addresses!