I am confuse about memory configuration, i have below questions.
if 32-bit os maximum virtual address is 4GB, When i have 4 gb of ram for 32-bit os, What about the virtual memory size ? is it required virtual memory or we can directly use physical memory ?
In 32-bit os 12 bits are offset because page size=4k i.e 2^12 and 2^20 for page addresses
What about 64-bit os, What is offset size ? What is page size ? How it calculated.
What is PAE? If enabled how to decide size of PAE, what is maximum and minimum size of extended memory.
Q.1
Ans:-
The 32-bit processor includes a 32-bit register, which can store 2^32 and the 64-bit processor includes a 64-bit register, which can store 2^64.
A 64-bit register can theoretically 16 exabytes of memory.
For 32-bit os maximum virtual memory is 4GB, it can address only up to 4GB of physical RAM (Without PAE).
For the Linux kernel, it works on virtual memory management i.e CPU address, There are many types of addresses For example. bus address, physical address(There are other concepts to access physical memory eg. DMA and IOMMU)
The virtual memory size is the maximum virtual size of a single process.
For more details of 32-bit and 64-bit processor use link.
Q.2
Ans:-
For 64-bit OS address space is 16 exabyte RAM. and generally page size is 8K i.e 2^13 (apart from that there is the concept of hugepages and hugetlb).
64-bit currently uses 48-bit physical addresses that allow you to address up to 256 TBytes of main memory. because the page table is also a page itself and consists of page table entries. Since the number of entries in one table is limited and depends on the entry size and page size, so tables are arranged in multiple levels. There are usually 2 or 3 levels, and sometimes even 4 levels.
General calculation of 64-bit os:-
Number of entries in page table = virtual address space size/page size
= 2^(64-13) (if page size is 8K)
= 2^51 for maximum page table entries (if you are using whole 64 bits)
Page Size == Frame Size.
Q.3
Ans:-
For PAE, the page table entry expands from 32 to 36 bits. This allows more space for the physical page address, or page frame number(PFN) field, in the page table entry. In the initial implementations of PAE, the page frame number(PFN) field was expanded from 20 to 24 bits. The size of the "byte offset" from the address being translated is still 12 bits, so total physical address size increases from 32 bits to 36 bits (from 20+12 to 24+12). This increased the physical memory that is theoretically addressable by the CPU from 4 GB to 64 GB.
Maximum size of PAE is = 64GB (2^36).
For PAE in details use link
I've looked at other answers, none of them convince me, most people just say because 2^32 = 4GB.
From my understanding, 32 bit address, means that each word is 32 bits long. Thus largest 32bit address can represent is 4294967296, which means a 32bit address can represent 4294967296 Words.
How does this 4294967296 Words translate into 4GB....?
Conventional PC Memory is divided into bytes, and each address points at a single byte (not a word). Since an address is 32 bits, we can have 2^32 = 4294967296 addresses, or 4294967296 bytes (B).
4294967296 B = 4194304 kB = 4096 MB = 4 GB, if we go by factors of 1024.
While CPUs use words internally, they still are able to address individual bytes in memory. Since a single memory address has to fit into a word to allow the CPU to handle it, you can only address up to 4 GiB of memory in a 32 bit system.
Non withstanding these remarks, there are ways to address more memory on a 32 bit processor. In x86 CPUs, this is handled under the Physical Address Extension (PAE) moniker. By using more then 32 address lines, you can address more memory. However, since the CPU still has only 32 bit words, you can still only use 4 GiB per page table (which is what the actual applications use).
I am new to computer architecture. So correct me if I am wrong.
If a memory module consists of 8 memory chips and if each chip stores 4bits per address then by applying an address to the address pin of the module I can get (8 x 4=) 32 bit from that address in the module. But byte addressing tells that every byte has an address. But here I am accessing 32bits using an address. So how is it possible?
I think if each chip stores 1bit per address then by applying an address to the module I can access 8bit or one byte.
You say each chip stores 4bits per address and you have 8 on the same address bus. It is the address bus that is the limiting factor. The address bus must have 32 lines for each byte in a 32 bit architecture to be addressable. If you have 8 chips each producing 4 bits in response to the same address, then you have 32bits per address. The advantage of such an arrangement would be the address bus lines could be reduced by 2 without decreasing the addressable range (only the resolution).
You are correct in thinking that each chip would need to produce 1 bit per address to allow byte addressing.
That's the theory, in practice I would suspect a solution could be architected where the 4 bits could be time division multiplexed making each individually accessible.
I have heard for a long time not to address less than 32 bits at a time, as that may be the smallest unit addressable. Certainly it would make sense when 2Gb-4Gb was the physical limit of 32 bit byte addressing.
I am confused with so many terminologies that my instructor talks about such as word,byte addressing and memory location.
I was under the impression that for a 32-bit processor,
it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
The way I think now is:
The memory is like an array of buckets each of 1 byte length.
when we say byte addressing (which I guess is the most common ones), each char is 1 byte and is retrieved from the first bucket (say for example).
for int the next 4 bytes are put together in little-endian ordering to compute the Integer value.
so each memory, I see it as, 8 bits or 1 byte, which can give upto 2^8 locations, this is far less than what cpu can address.
There is some very basic mis-understanding here on my part which if some experts can explain in simple terms that a prosepective CS-major student can it in once forever.
I have read various pages including this one on word and here the unit of address resolution is given as 8b for ARM, which adds more to my confusion.
The processor uses 32 bits to store an address. With 32 bits, you can store 2^32 distinct numbers, ranging from 0 to 2^32 - 1. "Byte addressing" means that each byte in memory is individually addressable, i.e. there is an address x which points to that specific byte. Since there are 2^32 different numbers you can put into a 32-bit address, we can address up to 2^32 bytes, or 4 GB.
It sounds like the key misconception is the meaning of "byte addressing." That only means that each individual byte has its own address. Addresses themselves are still composed of multiple bytes (4, in this case, since four 8-bit bytes are taken together and interpreted as a single 32-bit number).
I was under the impression that for a 32-bit processor, it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
This is typically not the case -- bit-level addressing is quite rare. Byte addressing is far more common. You could design a CPU that worked this way, though. In that case as you said, you would be able to address up to 2^32 bits = 2^29 bytes (512 MiB).
For one bit, You would have 0 or 1 and For two bits, you would have 00, 01, 10, 11. For 8 bits, you would have 2^8 which is 256 address values. Address and Data are separate terms. Address is the location and Data is the content in that location. Data width(content) is how many bits you could store in one memory cell address.(Think like an apartment with bedrooms- each apartment in a building has two bedrooms)and Data depth(address) is how many addresses you would have(In a building how many apartments you would have #1 thru #1400 etc). One bit in the CPU register can reference an individual byte in memory like one number in apartment number can reference one apartment. SIMM module RAMs had 32 bit Data width and DIMM modules have 64 bit Data width. It means in one memory address in DIMM, It stores 64 bits data. How many addresses can be multiplexed by two wires (two bit processing), you could make 4 addresses. (Each of these addresses could hold 64 bits if it is DIMM module ). 32 bit processing means, 32 wires, 2^32 address options. Even though, 64 bit processing has 64 bit registers and internal bus (wires) as 64 bit, http://www.tech-faq.com/address-bus.html, address bus max is 44 bits. means 2^44 maximum addressing can be achieved by Intel Super Server CPU Itanium 2.
Just reading some notes in a purdue lecture about OSs, and it says:
A program sees memory as an array of
bytes that goes from address 0 to 2^32-1 (0 to
4GB-1)
Why 4 GB?
Because 32 bits are able to represent numbers up to 232 − 1 = 4294967295 = 4 GiB − 1 and therefore address up to 232 individual bytes which would be 4 GiB then.
There are ways to circumvent that, though. For example using PAE even a 32-bit operating system can support more memory. Historically this has most commonly been used on servers, though. Also, the non-server Windows SKUs don't support it. By now all that is moot, though, given that 64-bit CPUs, OSes and driver support are commonplace.
Because each byte of memory has to have an address. In a 32-bit operating system, an address is 32 bits long; thus, there are 2^32 possible addresses, which means there are 2^32 bytes = 4 GB.
If you have a 4-bit system, this means the address for each byte is 4 binary digits, the probability of all your address will range from 0000 through 1111 which is 2^4 = 16 (2 because there is either 0 or 1), with four bits it's possible to create 16 different values of zeros and ones, If you have 16 different addr. each represent a byte then you can have a max of 16 bytes
4-bit system will look like this:
For a 32-bit system, your max is 2^32 = 4294967292 bytes
Everybody is saying 2^32 = 4GiB, which is right. Just in case, here is how we got there:
A 32-bit machine uses 32 bits to address memory. Each bit has a value of 0 or 1. If you have 1 bit, you have two possible addresses: 0 or 1.
A two-bit system ( pun aside ) has four possible address: 00 =0, 01=1, 10=2, 11=3. 2^2=4.
Three bits have 8 possble addresses: 000=0, 001=1, 010=2, 011=3, 100=4, 101=5, 110=6, and 111=7.
Each bit doubles the potential address space, which is why 2^n tells you how many addresses you use for a given number of bits. 2^1 = 2, 2^2 = 2*2 = 4, 2^3 = 2*2*2 = 8, etc.
By the time you get to 32 bits, you are at 4GiB.
4 GB = 2^32 bytes.
2 ^ 32 = 4 * 1024 * 1024 * 1024
That, in bytes, is the definition of 4 GB. In other words a 32-bit register as a memory pointer can address 4 GB of memory and no more.
Actually, it's not as simple as 2^32 = 4294967296 bytes. You see in x86 protected mode, with paging enabled (that is, what you get when you use any modern OS), you don't address memory locations directly, even though the paging translation mechanism is transparent for client applications.
Of a logical 32 bit memory address, when using 4K pages:
bits 22-31 refer to a page directory
bits 12-21 refer to a page table
bits 11-0 refer to an offset in the 4096 byte page
As you can see, you have 2^10 (1024) page directories, in each page directory, you have 2^10 page tables and each page is 2^12 (4096) bytes long, hence 2^32 = 4294967296 bytes. The width of the memory bus is conveniently the same as the word length of the CPU but it's not necessary to be like this at all. In fact, more modern x86 CPUs support PAE which enables addressing more than 4GB (or GiB) even in 32-bit mode.
32bits can represent numbers 0..2^32 = 0..4,294,967,296
32bits can address up to 2^32Bytes (assuming Byte-size blocks)
2^32Bytes is the max size
2^32B = 4,194,304KiB = 4,194MiB = 4GiB
Because is the amount of different memory addresses (in Bytes) that can be stored in a Word.
But, in fact, that's not always true (in most of cases it isn't), the OS can handle more physical memory than that (with PAE) and the applications can use less than 4GB of virtual memory (because part of that virtual memory is mapped to the OS, 1GB in Linux and 2GB in Windows, for example).
Another scenario where that doesn't apply is if the memory was addressed by Words instead of Bytes, then the total memory addressable would be 16GB, for example.
A CPU with 32 bit registers will need the operating system to calculate everything in chunks of 32 bits. It's a hardware requirement to which the OS must conform. Similarly, CPUs with 64 bit registers will need an operating system that reads and writes data from the RAM in chunks of 64 bits. (Every time you read data from memory, you need to read it into one of those registers - be it 32 bit, or 64 bit, or 16 bit, etc.)
A 32 bit register can store 2^32 different RAM addresses.
Each RAM address corresponds to a byte (8 bits) in modern RAMs. (The 4 GB argument is true only for those RAMs that have addresses for every byte.)
=> 2^32 = 4,294,967,296 addresses, → that corresponds to 4,294,967,296 bytes.
Now, 1 KB = 2^10 bytes or 1024 bytes (in the binary system)
Therefore, 4,294,967,296 bytes / 1024 = 4,194,304 KB
4,194,304 KB / 1024 = 4,096 MB
4,096 MB / 1024 = 4 GB
Mainly due to 32bit OS chosing to support only 2^32-1 addresses.
If the CPU has more than 32 address lines on the FSB, then the 32bit OS can choose to use a paging mechanism to access more than 4GiB. (For example Windows 2000 Advanced Server/Data Center editions on PAE supported Intel/AMD chips)
4 GB = 2^32 bytes.
But remember its max 4gb allocated by a 32 bit OS. In reality, the OS will see less e.g. after VRAM allocation.
As previously stated by other users, 32-bit Windows OSes use 32-bit words to store memory addresses.
Actually, most 32-bit chips these days use 36-bit addressing, using Intel's Physical Address Extension (PAE) model. Some operating systems support this directly (Linux, for example).
As Raymond Chen points out, in Windows a 32-bit application can allocate more than 4GB of memory, and you don't need 64-bit Windows to do it. Or even PAE.
For that matter, 64-bit chips don't support the entire 64-bit memory space. I believe they are currently limited to 42-bit space... the 36-bit space that PAE uses, plus the top 8-bit addresses,