I'm trying to publish to the topic /joy/set_feedback.
I had this in my include:
#include <sensor_msgs/JoyFeedbackArray.h>
I had my Nodehandle and Publisher like this :
feed_pub = nh->advertise<sensor_msgs::JoyFeedbackArray>("/joy/set_feedback", 1);
Now my problem is that i want to fill up the feed_msg
sensor_msgs::JoyFeedbackArray feed_msg;
In the documentation sensor_msgs/JoyFeedbackArray Message
it says it's an array. No matter what i did wrote there, I always get an error.
It would be very helpful if i could get a correct example to fill up this array.
I'll be needing a vibration signal with type: 1 / id: 0 / intensity: 1.0.
ROS messages can handle something like Arrays. But when you are working with a ROS Message-"Array" in Python or C++, you need to use a different data type. In your case, you need a std::Vector<sensor_msgs::JoyFeedback>.
For other cases, the ROS Wiki has created a table of translations between ROS Message, C++ and Python:
You can find a detailed explaination of the different datatypes and their conversion between ROS Message and Python or C++ here: http://wiki.ros.org/msg
I am working on new costume board based on (i. MX 6Solo6DualLite).and I use (TJA1100 100BASE-T1 PHY) for Automotive Ethernet..
please correct me if my questions don't make sense, or I am in the wrong way.
I want to write driver for this device.. and make sure that it works correctly.
1- I can make sure that the driver works properly in the U-boot step, Right? I mean no need to load Linux kernel, so I have just to add source code C driver in U-boot source code and compile it. I want to do this in U-boot step, so I can limit the numbers of files that initialise all peripheriques, and make it simple as possible since that U-boot can behave like (mini-Os)
2-I don't know how to write this driver (exactly..), so I am looking for the driver (source code) that initialise the Ethernet Controller in any other processor , and initialise another typeof ethernet phy, in order to get an idea and write a similar driver source code for I.MX6 and TJA1100,?
after this i think that i could maybe add some very basic file c For simple Protocol like ARP, for test purpose..
3- is this good idea writing driver code by inspiring from another driver code source?
4 - maybe, if you already have a driver for (i. MX 6Solo6DualLite and TJA1100 100BASE-T1 PHY) can you provide to me please... ?
for my second question i tried to extract from U-boot source code the C file that initialise Ethernet Controller in AM335x, and initialise LAN8710A phy,(in beaglebone black) in order to get an idea and write a similar driver source code but i couldn't found it .. i found network C file for protocol .... but that's disturp me i couldn't seperate them from the real C file that initialise ethernet controller and ethernent Phy .
http://www.denx.de/wiki/U-Boot/SourceCode
There is a driver published on the NXP forum:
https://community.nxp.com/thread/460767
It includes both some bare metal code that should be usable with U-Boot and a Linux driver.
I have an example design in system generator for image processing which has one input image and one output image.
I would like to send data through AXI stream interface and export it as an IP core to Vivado IP integrator and develop the design further using DMA and software in SDK.
Firstly is it possible to have AXI stream interface in my design? If yes, how can I implement it? Can anybody help me?
Thanks in advance.
(i have attached image of the example here)
Image_filter
Firstly is it possible to have AXI stream interface in my design?
Yes, it is.
If yes, how can I implement it? Can anybody help me?
I have a similar project develop in Vivado 2015.3: an image filter (created with "High Level Synthesis") and this design block:
The High Level Synthesis code should look like:
#include "top.h"
void hls_sobel(
hls::stream< ap_axiu<8,1,1,1> > &video_in,
hls::stream< ap_axiu<8,1,1,1> > &video_out
)
{
ap_uint<16> Image_w=IMAGE_W_MAX;
ap_uint<16> Image_h=IMAGE_H_MAX;
// Create AXI streaming interfaces for the core
#pragma HLS INTERFACE axis port=video_in bundle=video_in
#pragma HLS INTERFACE axis port=video_out bundle=video_out
// No control interface - auto-start as soon as there's an input frame
#pragma HLS INTERFACE ap_ctrl_none port=return // no handshakes
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> mat_in(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> mat_out(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> inx(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> iny(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> sobelx(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> sobely(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> zerox(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> zeroy(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> absx(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> absy(Image_h, Image_w);
#pragma HLS dataflow
// read input and convert from axi-stream to Mat
hls::AXIvideo2Mat(video_in, mat_in);
// calculate Sobel in X and Y directions
hls::Duplicate(mat_in, inx, iny);
hls::Sobel<1,0,3>(inx, sobelx);
hls::Sobel<0,1,3>(iny, sobely);
// calculate abs of said Sobel
hls::Zero(zerox);
hls::Zero(zeroy);
hls::AbsDiff(sobelx, zerox, absx);
hls::AbsDiff(sobely, zeroy, absy);
// add both abs
hls::AddWeighted(absx, 1, absy, 1, 0, mat_out);
// write output
hls::Mat2AXIvideo(mat_out, video_out);
}
As you can note, a DMA is used. For the Video-Image application, I recommend using a Video-DMA (VDMA) to send all the pixel information via streaming-interface. After, in the SDK, it is easy to manage the transfer using the function in the Board Support Package (BSP).
Also, you can note that in the code above is explicitly specified hls::stream< ap_axiu<8,1,1,1> > &video_in,! In this way, I am creating a streaming interface.
Here you can find a tutorial about HLS image processing filter. In the last page, there are useful links. Follow them to realize the same system of the example.
I hope this can help
I am currently working on a very similar project, (I am not using System Generator though), so I bet I could give you some pointers. As far as I remember SysGen can produce some VHDL or Verilog code of your design. So:
After you get the HDL code of your design, pack it as a new IP in Vivado. There are plenty of tutorials on how to do this, it should be easy with a little search. You should wisely choose the interfaces you want to implement. You're going to definitely need an AXI Stream Slave interface for accepting the incoming data and an AXI Stream Master interface to transmit the results.
After you package your IP, you can begin building your system block-by-block (there are also some good tutorials on this, see end of answer). You will need to use the AXI DMA IP (or the Video DMA, depending on your needs) and you'll have to configure it properly, like choosing register-mode or scatter-gather, channels, etc.
Be extremely careful to generate the proper AXI synchronization signals correctly, as they can totally ruin your design (and nerves). It's easy but it requires some study of the AXI documentation provided by Xilinx (ARM's docs are too complicated for my taste).
Finally, you will definitely find very useful information on the following resources:
Xilinx Forum
FPGAdeveloper's example
another AXI-stream based design example
FPGA note wiki
AXI DMA Product Guide
Channel of Dr. Sadri of TU Kaiserslautern, really helpful to deeply understand AXI design concepts
Good luck!
PS: Simulators are your friends! Never try implementing your freshly written code directly onto the system design. Modelsim can save you significant time and effort which would otherwise be spent on pointless debugging.
If I understand correctly, you want to know how to create an AXI Stream interface inside your system generator design.
Yes it is possible to do it. You should have atleast two inputs in your design with names, for example, image_tdata and image_tvalid (gateway in). When you generate IP core, sysgen will recoginize this as an AXI STREAM. The format is important. It must be "$customname_tdata" and "$customname_tvalid". You can add other inputs as well to add to the AXI STREAM such as "$customname_tlast", "$customname_tready".
How do I capture all the packets in radio range of a particular node in contiki?
While reading the contiki mailing lists and contiki github, I could read people saying something about making changes to core/dev/cc2420.c file. Some people spoke about setting or resetting values of CC2420_CONF_AUTOACK.
I nowhere found proper information regarding putting a node in promiscous mode. Please help.
I guess what you mean to do is to disable the hardware address filtering. There is a radio API for this in Contiki:
#include "dev/radio.h"
// ...
radio_value_t radio_rx_mode;
if(NETSTACK_RADIO.get_value(RADIO_PARAM_RX_MODE, &radio_rx_mode) == RADIO_RESULT_OK) {
radio_rx_mode &= ~RADIO_RX_MODE_ADDRESS_FILTER;
NETSTACK_RADIO.set_value(RADIO_PARAM_RX_MODE, radio_rx_mode);
}
You can also disable automatic acknowledgements by removing the RADIO_RX_MODE_AUTOACK bit of the rx_mode, but that's a different setting.
In a first phase, i collect a list of constraints. Then, i would like to store this "session", i.e. All the constraints but all the associated variables as well in a file so that I can, in a second phase, read back the constraints and assert them, or even negate some of them before asserting.
What is the best way (fast and reliable) to store such a "session" in a file, and read it back ? Would the Z3_parse_smtlib2_file() API be the right way ? I have tried the Z3_open_log() API, but I don't find the API to read the log file generated by Z3_open_log(). And what about z3_log_replay(). This API does not seem to be exposed yet.
Thanks in advance.
AG
The log file created by Z3_open_log() can be replayed with Z3.exe (stand alone interpreter, not the lib) through the command line option /log myfile. As of today, I haven't seen any API in Z3 library that allows such a replay. For the time being, I have understood that the replay is deemed for debug analysis.
However, you can hack the library (just expose the z3_replayer class in z3_replayer.h) and use it to replay any log file, it is quite easy. The source code of my little feasibility-proof is given below, and is working fine as far as I know. I think it is very nice to be able to do that because sometimes I need to replay a session for debugging purpose. It is good to be able to replay it from a file, rather than from my whole program which is a bit heavy.
Any feedback would be very welcome. Also I would be interested to know whether this functionality could be integrated in the lib, or not.
AG.
#include <fstream>
#include <iostream>
#include "api/z3_replayer.h"
int main(int argc, char * argv[])
{
const char * filename = argv[1];
std::ifstream in(filename);
if (in.bad() || in.fail()) {
std::cerr << "Error: failed to open file: " << filename << "\n";
exit(EXIT_FAILURE);
}
z3_replayer r(in);
r.parse();
Z3_context ctx = reinterpret_cast<Z3_context>(r.get_obj(0));
check(ctx,Z3_L_TRUE); // this function is taken from the c examples
return 0;
}