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I'm trying to learn the ins and outs of an 8237A-5 DMA controller. I've been reading about it and now I've started to design it at the gate level in software. The CS pin is active low. If it gets a high signal on here, do what happens? Do all the other pins just go to high Z? What happens when it gets a low signal?
The data outputs go high impedance to allow other chips to use the data bus -- any operations that occur on the bus are ignored. When it gets a low signal on the CS pin, it will process any bus transactions it sees according to its data sheet. It will then latch the data from the data bus or drive data onto the data bus for a read or write cycle respectively.
The usual hardware design is the CS pin is driven by the output of the address decoder. When the address is seen to be in range for the target device, the address decoder drives that device's chip select pin active. That way, only the target device responds to each bus operation.
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When Bus off state occurs, assume because of failure of can controller in one node, then how other nodes will come to know that the bus is in off state?
Can anybody aware of this?
Bus off simply means that the current node stops sending information on the bus. Not necessarily that "the whole bus is off", though of course if there's some physical problem with the bus, then all nodes will end up in "bus off" state.
Other nodes will only notice this when a particular node stops responding and not doing ACK. Usually higher layer protocols have mechanisms for checking this, like for example the "Heartbeat" feature of CANopen.
For general CAN bus error handling see this: https://www.kvaser.com/about-can/the-can-protocol/can-error-handling/
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I interested in CAN HW object.
I aware of CAN Acceptance filter that in change of CAN ID filtering.
why CAN hardware acceptance filter present in receive?
When CAN message received, is CAN arbitration procedure excuted?
When CAN Message transmitted, Is CAN arbitration unnecessary?
Acceptance filters are used to filter received CAN messages according to their IDs, so that the firmware is not interrupted by the messages which it isn't interested in. Filters are applied after the hardware receives the message. If the message can't pass any filter, it's discarded. This prevents unnecessary hardware interrupts.
TX side doesn't need any filters, because the firmware designer chooses what to send.
Each node executes the CAN arbitration procedure during transmit, by sampling the bus as it transmits. If the transmitting node looses the arbitration, it stops transmitting to try again later.
Nodes on the bus receive only the messages that won the arbitration. Arbitration process is an essential & embedded part of the CAN protocol and it's always there and necessary.
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Is it (really) possible to sync time across multiple (not inter-connected) iOS devices to within a few milliseconds accuracy? The only possible solution I (and others, according to Stack Overflow) can think of is sync the devices with a time server(s) over NTP.
Multiple sources state:
NTP is intended to synchronize all participating computers to within a
few milliseconds of Coordinated Universal Time (UTC). It uses the
intersection algorithm, a modified version of Marzullo's algorithm, to
select accurate time servers and is designed to mitigate the effects
of variable network latency. NTP can usually maintain time to within
tens of milliseconds over the public Internet, and can achieve better
than one millisecond accuracy in local area networks under ideal
conditions. Asymmetric routes and network congestion can cause errors
of 100 ms or more.
Can NTP really achieve accuracy within the few milliseconds level?
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How does having unique Data & Instructions memory affects us to the standard 5-stage Pipeline?What about with & without Forwarding?
What's the advantage of having a different memory for each?
Regardless of having Forwarding, if you only have one port to access memory (e.g. unique Data & Instruction memory bus) and to simplify let's say there is no cache in the system (so every memory access needs to use the memory unit) then every instruction that needs the MEM stage to use the memory bus will generate a structural hazard, as the CPU won't be able to perform the FETCH and MEM stages in parallel because they both need to access memory.
If instead you have two ports to access memory (e.g, one for Instructions and another for data), then the structural hazard noted above will be avoided as each memory-access stage will use its own bus+memory.
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I'm not sure, if it's the right place here to ask this question.
But can anybody explain more detaild, how sim-based mobile phone tracking's working, und if it costs anything (the second part is very important)?
The Wikipedia article explains it pretty well:
Mobile phone tracking tracks the current position of a mobile phone even on the move. To locate the phone, it must emit at least the roaming signal to contact the next nearby antenna tower, but the process does not require an active call. GSM localisation is then done by multilateration based on the signal strength to nearby antenna masts.
So as soon as your phone is turned on, it starts to emit signals that the antennas catch. If several of them receive the signal, that (and the signal strength) gives a pretty good indication of your location.
It needs a bit of software (which the law requires today), so it doesn't cost anything "extra" for the people that provide the hardware. It's not free for normal people to use, though.
sim based? mobile phone tracking goes in layers, just like PC. At first GPS, if phone don't have it then it counts what mobile providers towers covers the phone and how strong mobile signal is from each tower, so by that it can counts you location. It Don't cost for telephone companies but it might for you since it depends on connection provided by towers. So its not the thing you can do without providers knowing it.