I've stumbled across a problem:
How many bits are needed to address a 10kB data memory if one cell is 1 byte in size?
so when I try to solve this question the only thing I can solve is what's the amount of cells but not how many bits are needed to address a 10kB data memory.
Because what I have come up with is that the answer must be 81920/8=10240 cell amount but I'm pretty sure it's wrong because it answers the last part of the question and not how many bits.
Think of a cell as a minimal entity that can be uniquely accessed / addressed. You have 10240 such cells, so the address width must be able to represent up to that value. E.g. 8 bit wide address (noun) can address (verb) 256 unique entities, 10 bit wide address can address 1024 unique entities, etc.
Back in the days of 32-bit PCs, each process can have at most 4GB virtual memory exactly because the virtual address width was 32 bits, and the “minimal entity” addressable was a byte. So 2^32 bytes is the maximum addressable memory size for those PCs.
Related
I am a a bit confused on the notion of "size" when it comes to ram sizes and page sizes (in paging memory management scheme), or anytime we are measuring a range of addresses in "bytes".
My confusion comes from the fact that on a x64 system, I am assuming the main bus is 64 bits and the amount of "locations" which can be referenced by the memory address register is 2^64 (18,446,744,073,709,551,616 individual addresses).
Now, if I have a page size or some ram that is 1kb, what does this mean exactly? I am under the assumption that this means that each page will encompass a range of 1000 (or 1024?) addresses. But then what does the "byte" part of 1 kilo "byte" even have to do with anything? Clearly the address itself is not a "byte" in length (it would be 64 bits in length for a x64 system). Is it just saying that the addresses themselves hold one byte of memory each? This seems funny to me if this is the case, seems like we should talk about page and ram sizes in terms of a raw "flat number" like 1024, and a refer to them like "the pages are each 1024 addresses in length", and NOT like "the pages are each 1024 bytes in length".
Any help or clarification is greatly appreciated, thanks!
I am new to computer architecture. So correct me if I am wrong.
If a memory module consists of 8 memory chips and if each chip stores 4bits per address then by applying an address to the address pin of the module I can get (8 x 4=) 32 bit from that address in the module. But byte addressing tells that every byte has an address. But here I am accessing 32bits using an address. So how is it possible?
I think if each chip stores 1bit per address then by applying an address to the module I can access 8bit or one byte.
You say each chip stores 4bits per address and you have 8 on the same address bus. It is the address bus that is the limiting factor. The address bus must have 32 lines for each byte in a 32 bit architecture to be addressable. If you have 8 chips each producing 4 bits in response to the same address, then you have 32bits per address. The advantage of such an arrangement would be the address bus lines could be reduced by 2 without decreasing the addressable range (only the resolution).
You are correct in thinking that each chip would need to produce 1 bit per address to allow byte addressing.
That's the theory, in practice I would suspect a solution could be architected where the 4 bits could be time division multiplexed making each individually accessible.
I have heard for a long time not to address less than 32 bits at a time, as that may be the smallest unit addressable. Certainly it would make sense when 2Gb-4Gb was the physical limit of 32 bit byte addressing.
I need help understanding memory. How many bytes can be stored in a memory unit that uses 8 address bits and a 16 bit architecture?
I think it's 2^8 = 256. Is this correct?
Edit: I mean 256
It depends.
Firstly "16 bit architecture" is too vague to be a helpful characterization for this problem. A characterization like that generally refers to the width of registers and data paths (e.g. in the ALU), not how memory is addressed.
Secondly, the answer actually depends on whether the addresses are byte addresses or "word" addresses. AFAIK "almost all" new processor / instruction set architectures designed since the 1980's have used byte addresses. But prior to that it was common for addresses to address words of up to 60 bits (or possibly more).
But assuming byte addressing, then an 8 bit address allows you to address 2^8 bytes; i.e. 256 bytes.
On the other hand, if we assume word addressing with a 16 bit word, then 8 bit addresses will address 256 words ... which is 512 bytes.
The base answer is the 2^number of bits. However,long ago sixteen bit systems came up with means for accessing more than 2^16 memory though segments. While an application can only access 2^16 bytes at a time, changing the values in hardware registers allows the application to change which 2^16 bytes of a larger address space are being accessed.
You typically do things like
Map buffer 1 to the address space.
Queue a read operation to the buffer.
Map another buffer 2 to the address space.
Read operation completes-map Buffer 1 back so that the data can be accessed.
Im trying to learn about memory addressing (this is for Uni) and im unsure about the effect that a word addressable memory would have when i need to calculate number of address bits.
I will explain what (i think) I understand first.
To calculate the number of address bits I use : log2(n) where n is the number of bits of the memory.I.e for 1gb (1024mb * 1024 * 1024)= 1073741824 bits so therefore log2(1073741824 ) = 30 meaning a 1gb memory would require 30 address bits. I think im understanding that correctly.
The part im not sure about is byte addressable memory versus word addressable memory and how it might effect the number of address bits.
THE QUESTION:
Is it that the above example is correct ONLY for byte addressable and if for instance a memory was word addressable and using 16 bit or 32 bit words then the number of address bits required would be less (1/2 or 1/4 in the case of 16 and 32 bit words)??
My thinking is that if a cel holds 8 bits in a byte addressable machine then a cel in word addressable memory would hold 16bits or 32bits and therefore the address bits required should be less.
Further notes - I am aware that most memory nowadays is byte addressable and that word size in a computer is specific to the processor / bus , but the problems im working on do not mention and just ask about the effect byte /word addressable would have.
I have searched for other questions on this and not found one that answers it (or that i understand to answer it) . This for examplehttps://stackoverflow.com/questions/19528750/byte-word-addressable actually seems to be asking a similar thing but the OP seems to have posted the question incorrectly by specifying that the memory is 4M x 16 (instead of 4mb x 16bit) leading people to calculate the memory as 64mb.
First off, you need to be careful with you bits and bytes, the original example you have seems to deal with bits, each you really seem to want to know about bytes. It does matter when we are dealing with a bit addressable memory or a byte addressable memory. So, lets talk about things in terms of byte addressable or word addressable memory.
As stated, your analysis of how to get the number of bits needed to address a memory is correct; but it can be generalized. In order to get the minimum number of bits we need to fully address a memory, we need to know how many unit-size things we can address. In your case, you were calculating the number of addresses need to address a 1 Gb (giga-bit) memory. We can just as easily do it in bytes, in order to byte address a 1 GB (giga-byte) memory, you need to know the number of addressable things (bytes) there are and then take the log2 of it. So, number of things there are is easy to get, (1 GB has 1024^3 or 1 G bytes in it) so we just need to log2 that; log2(1 G) = log2(1024*1024*1024) = 3*log2(1024) = 3 * 10 = 30. So, we need 30 bits to fully address that space.
Now lets talk in words. First is knowing the word size. Word size is not strictly 32 or 16 bits, it can be a range of values, typically dependent on whatever the processor decides to call a word (or the spec that is). Lets deal in 32-bit words for our example.
Now that we have a word size, we need to know the memory size. Lets assume the same 1 GB from before, but now we are word addressing it (its a word addressable memory now and the word size is 32 bits or 4 bytes). So, just as before, we need to know the number of addressable things (now its words) that there are in the memory size. Well, this time it isnt 1 G, because our addressable thing is now 4 B in size instead of 1 B. So we need to take our 1 GB memory size and divide it by the word size (1 GB / 4 B = 0.25 G). Just as before, now that we have the number of addressable things (0.25 G), we just need to that the log2 of it; log2(0.25G) = log2 (256*1024*1024) = log2(256) + 2*log2(1024) = 8 + 2 * 10 = 28.
It all some down to the number of the addressable things (words, bytes, bits) in a given memory. As we typically give memory sizes in bytes, byte addressable calculations are easy, but the others just take a little manipulation to get something from a dimensional value (1 GB) into dimensionless value (1 G, ie 1024^3).
I am confused with so many terminologies that my instructor talks about such as word,byte addressing and memory location.
I was under the impression that for a 32-bit processor,
it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
The way I think now is:
The memory is like an array of buckets each of 1 byte length.
when we say byte addressing (which I guess is the most common ones), each char is 1 byte and is retrieved from the first bucket (say for example).
for int the next 4 bytes are put together in little-endian ordering to compute the Integer value.
so each memory, I see it as, 8 bits or 1 byte, which can give upto 2^8 locations, this is far less than what cpu can address.
There is some very basic mis-understanding here on my part which if some experts can explain in simple terms that a prosepective CS-major student can it in once forever.
I have read various pages including this one on word and here the unit of address resolution is given as 8b for ARM, which adds more to my confusion.
The processor uses 32 bits to store an address. With 32 bits, you can store 2^32 distinct numbers, ranging from 0 to 2^32 - 1. "Byte addressing" means that each byte in memory is individually addressable, i.e. there is an address x which points to that specific byte. Since there are 2^32 different numbers you can put into a 32-bit address, we can address up to 2^32 bytes, or 4 GB.
It sounds like the key misconception is the meaning of "byte addressing." That only means that each individual byte has its own address. Addresses themselves are still composed of multiple bytes (4, in this case, since four 8-bit bytes are taken together and interpreted as a single 32-bit number).
I was under the impression that for a 32-bit processor, it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
This is typically not the case -- bit-level addressing is quite rare. Byte addressing is far more common. You could design a CPU that worked this way, though. In that case as you said, you would be able to address up to 2^32 bits = 2^29 bytes (512 MiB).
For one bit, You would have 0 or 1 and For two bits, you would have 00, 01, 10, 11. For 8 bits, you would have 2^8 which is 256 address values. Address and Data are separate terms. Address is the location and Data is the content in that location. Data width(content) is how many bits you could store in one memory cell address.(Think like an apartment with bedrooms- each apartment in a building has two bedrooms)and Data depth(address) is how many addresses you would have(In a building how many apartments you would have #1 thru #1400 etc). One bit in the CPU register can reference an individual byte in memory like one number in apartment number can reference one apartment. SIMM module RAMs had 32 bit Data width and DIMM modules have 64 bit Data width. It means in one memory address in DIMM, It stores 64 bits data. How many addresses can be multiplexed by two wires (two bit processing), you could make 4 addresses. (Each of these addresses could hold 64 bits if it is DIMM module ). 32 bit processing means, 32 wires, 2^32 address options. Even though, 64 bit processing has 64 bit registers and internal bus (wires) as 64 bit, http://www.tech-faq.com/address-bus.html, address bus max is 44 bits. means 2^44 maximum addressing can be achieved by Intel Super Server CPU Itanium 2.