Im trying to learn about memory addressing (this is for Uni) and im unsure about the effect that a word addressable memory would have when i need to calculate number of address bits.
I will explain what (i think) I understand first.
To calculate the number of address bits I use : log2(n) where n is the number of bits of the memory.I.e for 1gb (1024mb * 1024 * 1024)= 1073741824 bits so therefore log2(1073741824 ) = 30 meaning a 1gb memory would require 30 address bits. I think im understanding that correctly.
The part im not sure about is byte addressable memory versus word addressable memory and how it might effect the number of address bits.
THE QUESTION:
Is it that the above example is correct ONLY for byte addressable and if for instance a memory was word addressable and using 16 bit or 32 bit words then the number of address bits required would be less (1/2 or 1/4 in the case of 16 and 32 bit words)??
My thinking is that if a cel holds 8 bits in a byte addressable machine then a cel in word addressable memory would hold 16bits or 32bits and therefore the address bits required should be less.
Further notes - I am aware that most memory nowadays is byte addressable and that word size in a computer is specific to the processor / bus , but the problems im working on do not mention and just ask about the effect byte /word addressable would have.
I have searched for other questions on this and not found one that answers it (or that i understand to answer it) . This for examplehttps://stackoverflow.com/questions/19528750/byte-word-addressable actually seems to be asking a similar thing but the OP seems to have posted the question incorrectly by specifying that the memory is 4M x 16 (instead of 4mb x 16bit) leading people to calculate the memory as 64mb.
First off, you need to be careful with you bits and bytes, the original example you have seems to deal with bits, each you really seem to want to know about bytes. It does matter when we are dealing with a bit addressable memory or a byte addressable memory. So, lets talk about things in terms of byte addressable or word addressable memory.
As stated, your analysis of how to get the number of bits needed to address a memory is correct; but it can be generalized. In order to get the minimum number of bits we need to fully address a memory, we need to know how many unit-size things we can address. In your case, you were calculating the number of addresses need to address a 1 Gb (giga-bit) memory. We can just as easily do it in bytes, in order to byte address a 1 GB (giga-byte) memory, you need to know the number of addressable things (bytes) there are and then take the log2 of it. So, number of things there are is easy to get, (1 GB has 1024^3 or 1 G bytes in it) so we just need to log2 that; log2(1 G) = log2(1024*1024*1024) = 3*log2(1024) = 3 * 10 = 30. So, we need 30 bits to fully address that space.
Now lets talk in words. First is knowing the word size. Word size is not strictly 32 or 16 bits, it can be a range of values, typically dependent on whatever the processor decides to call a word (or the spec that is). Lets deal in 32-bit words for our example.
Now that we have a word size, we need to know the memory size. Lets assume the same 1 GB from before, but now we are word addressing it (its a word addressable memory now and the word size is 32 bits or 4 bytes). So, just as before, we need to know the number of addressable things (now its words) that there are in the memory size. Well, this time it isnt 1 G, because our addressable thing is now 4 B in size instead of 1 B. So we need to take our 1 GB memory size and divide it by the word size (1 GB / 4 B = 0.25 G). Just as before, now that we have the number of addressable things (0.25 G), we just need to that the log2 of it; log2(0.25G) = log2 (256*1024*1024) = log2(256) + 2*log2(1024) = 8 + 2 * 10 = 28.
It all some down to the number of the addressable things (words, bytes, bits) in a given memory. As we typically give memory sizes in bytes, byte addressable calculations are easy, but the others just take a little manipulation to get something from a dimensional value (1 GB) into dimensionless value (1 G, ie 1024^3).
Related
I'm reading this book 3 easy pieces by remzi. In chapter 18 paging introduction in the first paragraph it is written
(real address spaces are much bigger, of course,
commonly 32 bits and thus 4-GB of address space, or even 64 bits)
Now if 1 byte is 8 bits, shouldn't 32 bits be 32/8 4 bytes space? I have seen the math for getting the answer as 4GB
2^10 = 1KB
2^10 = 1MB
2^10 = 1GB
But then this is assuming 2^1 = 1B, But isn't this simply wrong?
What am I missing? What does my answer (4Bytes) represent here?
This question is related How many bits are needed to address this much memory?
But doesn't address why my math is incorrect. (OP there also has the exact same confusion).
Lets say that I change the word size to 64MB (wild I know). Then number of words is 1. According to the answers, number of bits would be 2^0 = 1, 0 bits? Then where and when do we use the fact that 1 byte = 8 bits?
Any help would be appreciated.
Today, RAM is byte addressable. Each address put on the address bus returns 1 byte. If you have 32 bits, the amount of different addresses that you can come up with is 2^32 = 4,294,967,296. Since you can have that much different addresses, then you can address that much bytes. In terms of bytes, this amount of bytes is called 4 GB.
Let's say a computer can hold a word size of 26 bits, I'm curious to know how many memory addresses can the processor generate?
I'm thinking that the maximum number it can hold would be 2^26 - 1 and can have 2^26 unique memory addresses.
I'm also curious to know that if let's say that each cell in the memory has a size of 12 bits then how many bytes of memory can this processor address?
My understanding is that in most cases a processor can hold up to 32 bits which is 4 bytes and each byte is 8 bits. However, in this case, each byte would be 12 bits and the processor would be able to address 2^26/12 bytes of memory. Is that safe to say?
I'm thinking that the maximum number it can hold would be 2^26 - 1 and can have 2^26 unique memory addresses.
I agree. We usually refer to this as the size of the address space.
As for the next question:
These days, the term byte is generally agreed to means 8 bits, so 12 bits would mean 1.5 bytes. It is a matter of terminology, though, which has varied in the long past.
So, I would say 226 12-bit words is capable of holding/storing 226 * 1.5 bytes, though they are not individually addressable, and would have to be packed & unpacked to access the separate bytes.
The DEC PDP-8 computer was a 12 bit computer and word addressable, so there were multiple schemes for storing characters: two 6 bit characters in a 12 bit word, and also 1 & 1/2 8-bit characters in a 12-bit word, so three 8-bit characters in two 12-bit words.
Similar issues occur when storing packed booleans in a memory, where each boolean takes only a single bit, yet the processor can access a minimum of 8 bits at a time, so must extract a single bit from a larger datum.
Assuming the structure starts at address/index 1000 in a byte addressable memory - how will the system work? Is this byte/word addressable it just for the sake of naming and ease of access? How does the processor acknowledges that the next address has started?
For processors that are byte addressable (which is all processors that I am aware of), the smallest granularity for a data access is a single byte. Although accesses are typically done at a larger word granularity (usually 4 or 8 bytes).
If you want to load 10 consecutive bits starting at address 0x1000 you would needed to load the first byte from address 0x1000 and the second byte from address 0x1001. However, for the second byte you would also need to use some operation to mask off the unwanted bits.
Another thing to note is that the register size in the CPU is usually either 32 or 64 bits. A 10 bit structure would be difficult to work with and is not something that you are likely to see in practice.
I'm reading a book about assembly; Jones and Bartlett Publishers Introduction to 80x86 Assembly
The author give exercises but no answers to it. Obviously before going further, I want
to make sure that I fully understand the chapter concepts.
donc,
What is the 8-hex-digit address of the "last" byte for a PC with 32 MBytes of RAM
This is my solution:
1) convert to bits
32 MBytes = 268435456 bits
2) I subtract 8 bits to remove the last byte
268435448
3) conversion to hexadecimal
FFFFFF8
So I got FFFFFF8
Does this look a good answer?
No. For assembly programming it's very helpful to be able to do simple power-of-2 calculations in your head. 1K is 2^10. So 1M is 2^20. So 32M is 2^25 (because 2^5 = 32). So the address of the last byte is 2^25-1 (because the first byte is at 0). This is 25 bits that are all 1's (because 2^n-1 is always n 1's). In hex, this is six F's (4 bits per F) plus an additional 1, so prepending a zero to get 8 hex digits, you have 01FFFFFF.
There are two things you should think about:
For most computers (all PCs) adresses are given in bytes, not in bits.
Therefore you must calculate: 32 MByte = 33554432 Bytes, minus 1 byte = 01FFFFFF (hex) as "Gene" wrote in his answer.
In reality (if you are interested in) you must also think about the fact that there is a "gap" in the address area (from 000A0000 to 000FFFFF) of real PCs so either not all the RAM is useable or the last address of the RAM comes later. This area is used for the graphics card and the BIOS ROM.
I thinking is : 00007FFF
because: 32MB = 32*1024 = 32768
byte last have address 32767 (7FFF)
I am confused with so many terminologies that my instructor talks about such as word,byte addressing and memory location.
I was under the impression that for a 32-bit processor,
it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
The way I think now is:
The memory is like an array of buckets each of 1 byte length.
when we say byte addressing (which I guess is the most common ones), each char is 1 byte and is retrieved from the first bucket (say for example).
for int the next 4 bytes are put together in little-endian ordering to compute the Integer value.
so each memory, I see it as, 8 bits or 1 byte, which can give upto 2^8 locations, this is far less than what cpu can address.
There is some very basic mis-understanding here on my part which if some experts can explain in simple terms that a prosepective CS-major student can it in once forever.
I have read various pages including this one on word and here the unit of address resolution is given as 8b for ARM, which adds more to my confusion.
The processor uses 32 bits to store an address. With 32 bits, you can store 2^32 distinct numbers, ranging from 0 to 2^32 - 1. "Byte addressing" means that each byte in memory is individually addressable, i.e. there is an address x which points to that specific byte. Since there are 2^32 different numbers you can put into a 32-bit address, we can address up to 2^32 bytes, or 4 GB.
It sounds like the key misconception is the meaning of "byte addressing." That only means that each individual byte has its own address. Addresses themselves are still composed of multiple bytes (4, in this case, since four 8-bit bytes are taken together and interpreted as a single 32-bit number).
I was under the impression that for a 32-bit processor, it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
This is typically not the case -- bit-level addressing is quite rare. Byte addressing is far more common. You could design a CPU that worked this way, though. In that case as you said, you would be able to address up to 2^32 bits = 2^29 bytes (512 MiB).
For one bit, You would have 0 or 1 and For two bits, you would have 00, 01, 10, 11. For 8 bits, you would have 2^8 which is 256 address values. Address and Data are separate terms. Address is the location and Data is the content in that location. Data width(content) is how many bits you could store in one memory cell address.(Think like an apartment with bedrooms- each apartment in a building has two bedrooms)and Data depth(address) is how many addresses you would have(In a building how many apartments you would have #1 thru #1400 etc). One bit in the CPU register can reference an individual byte in memory like one number in apartment number can reference one apartment. SIMM module RAMs had 32 bit Data width and DIMM modules have 64 bit Data width. It means in one memory address in DIMM, It stores 64 bits data. How many addresses can be multiplexed by two wires (two bit processing), you could make 4 addresses. (Each of these addresses could hold 64 bits if it is DIMM module ). 32 bit processing means, 32 wires, 2^32 address options. Even though, 64 bit processing has 64 bit registers and internal bus (wires) as 64 bit, http://www.tech-faq.com/address-bus.html, address bus max is 44 bits. means 2^44 maximum addressing can be achieved by Intel Super Server CPU Itanium 2.