My book had the following image:
And a question of how many PTE's are there in L2 (or L1), the answer was 16 = 2^4 but why is that?
In the question it's given that each PTE size is 2 bytes so the answer should be 2^4/2 = 8 Since L2 index holds where we will point to. For example if it's 2 then it point to second half of the first PTE and not the second PTE.
What am I missing here?
You are overthinking. There are 4 bits used to index the L1 page table entry, so there are 2^4 possible values for this index and thus 2^4 possible page tables entries.
The size of a page table entry is not relevant to this question. It is asking "how many", not "how large".
Related
I'm reading about virtual memory and I have some doubts reguarding multi-level paging.
I saw that in a N-level page table, the N-1 tables are used to store indexes to the next level tables.
This is my point:
Assuming the case of RISC-V Sv39 (Section 4.4 of RISC-V privileged architecture). We have the physical address of 1-level page root in SATP.ppn.
Virtual address is composed as follows:
<38-29> VPN[2] (9 bits)
<28-21> VPN[1] (9 bits)
<20-12> VPN[0] (9 bits)
<11-0> offset (12 bits)
After a TLB-miss, a page walk starts:
index_to_second_level_PT = SATP.PPN + VPN[2]
index_to_third_level_PT = index_to_second_level_PT + VPN[1]
physical_address = index_to_third_level + VPN[0]
My questions is:
Do all the idexes in the PTE (i.e, computed in step 1., 2., and 3.) are physical addresses? this makes sense to me, since once we get the physical address of the next table we can retrieve it from physical memory.
Moreover, always in RISC-V manual, also physical addresses and PTE entries are formatted with multiple fields (PPN[0], PPN[1], and PPN[2]). I understand that the virtual address is partitioned into three 9-bit fields to index the multi-level page table, but I don't understand why also the physical address is partitioned in such way.
Thanks in advance to anyone who responds.
I understand why a multi-level page table saves memory. In the classic 32-bit example, the size of each Page Table Entry (PTE) in a single-level table is 32 bit (4 Bytes). The fact that 20 of the 32 bits are used for page number means there are 2^20 (~1M) possible entries in this table. The total size of a single-level table is therefore 4 Bytes * 1M = 4MB.A two-level page table requires less memory because it does not need all of the second-level pages at the same time.
However, in a lot of examples for the calculations of two-level page table on the internet, people still use 4 Bytes to indicate the size of each PTE. Since we are only accessing 10 of the 32 bits at the first level, shouldn't the size of these PTEs be smaller than 4 Bytes?
The virtual address is broken to 10-10-12 first 10 bits are an index in the first level page table, there, you will find the address of the second level page table, which you index with the seconds 10 bits to find the start of the physical frame which you index with the remaining 12 bits.
Actually each entry contains the number of the virtual page (there are 2^20 such pages) and 12 flag bits.
We have question:
Calculate the maximum and minimum sizes of a single 3-level page table
for a 32-bit machine with a 4kB page size. The partitioning of the 20
bits representing a virtual page in this 3-level pge table is: (7, 7,
whatever bits remain).
I understand that minimum size should be 4k+4k+4k=12k because a process needs to have at least one frame allocated for itself. However I'm confused as to how to calculate the maximum. It works nicely with 2-level page tables because we can slice the 20 bits into 10 and 10 which works out nicely to 1024 entries * 4 bytes each which is a nice factor of 4k. But with 2^7 entires we get a strange number, any ideas on how to solve? Thanks.
Sadly, your question does not have an answer. This type of question is typical of the horrible operating systems textbooks out there.
First of all, you have no indication of the page table entry. Is is 32bits? 64bits? Are the entries the same size at each level of the page table?
It's not really possible for a process to have a 0-byte page table. There would need to be a least one page mapped for the process to executive. A minimum would then be 3 page table entries of whatever unspecified size (probably something like 12-bytes).
At to the maximum, that depends upon how the hardware and OS divides up the address space.
First of all, this is not language tag spam, but this question not specific to one language in particulary and I think that this stackexchange site is the most appropriated for my question.
I'm working on cache and memory, trying to understand how it works.
What I don't understand is this sentence (in bold, not in the picture) :
In the MIPS architecture, since words are aligned to multiples of four
bytes, the least significant two bits are ignored when selecting a
word in the block.
So let's say I have this two adresses :
[1........0]10
[1........0]00
^
|
same 30 bits for boths [31-12] for the tag and [11-2] for the index (see figure below)
As I understand the first one will result in a MISS (I assume that the initial cache is empty). So one slot in the cache will be filled with the data located in this memory adress.
Now, we took the second one, since it has the same 30 bits, it will result in a HIT in the cache because we access the same slot (because of the same 10 bits) and the 20 bits of the adress are equals to the 20 bits stored in the Tag field.
So in result, we'll have the data located at the memory [1........0]10 and not [1........0]00 which is wrong !
So I assume this has to do with the sentence I quote above. Can anyone explain me why my reasoning is wrong ?
The cache in figure :
In the MIPS architecture, since words are aligned to multiples of four
bytes, the least significant two bits are ignored when selecting a
word in the block.
It just mean that in memory, my words are aligned like that :
So when selecting a word, I shouldn't care about the two last bits, because I'll load a word.
This two last bits will be useful for the processor when a load byte (lb) instruction will be performed, to correctly shift the data to get the one at the correct byte position.
I have been given the format for page table entries:
Bit 23: Valid Bit
Bit 22: Modify Bit
Bits 22-18: LRU Bits
Bits 17-0: Frame Number
Im told that the system uses 32-bit virtual addresses and pages that are 8192 bytes in size.
What would be the total size in bytes of the page map table?
If an inverted page map table is used what would be its total size in bytes if the LRU field within each PTE is reduced to 3 bits?
I have been helped with this problem, and calculated that the maximum physical memory of the system is 2GB. I'm not sure if I need to take the 32 bit virtual address data given into consideration when calculating the total size of the page map table.
Looks like there isn't enough information to answer this question.
See, the page table size is equal to the number of entries in it times the size of each entry.
First, I don't know if the page table entries are 24-bit-long or 32-bit-long or bigger. That's not explicitly specified.
Second, if there's only one page table involved in translation of virtual addresses into physical addresses, a page table has to cover the entire 32 bits of the virtual address. Since a single PTE only handles 13 (because the page size is 2^13=8192 bytes), you'd need 2^(32-13)=2^19 entries in this case.
Now, if there's a hierarchy of page tables involved in the translation, in other words, the entries of the first page table (often called page directory) point to a second-level page table and those either point to the code/data pages or to a third-level page table and so on, you get the idea... in this case the answer is going to be different. But it's not specified whether there's just one page table or a chain of multiple page tables.
In my opinion, a page table of 2^19 entries is unlikely. A page table is usually the size of a single page (sometimes smaller). So, if, for example, PTEs are 32-bit, you have 8192/4=2048 PTEs in a PT and that covers only 11 (2^11=2048) out of the remaining 32-13=19 bits of the virtual address. The other 19-11=8 bits of the virtual address must be taken care of by another page table, page directory, having only 2^8=256 entries, provided the entries are the same in the page table and page directory.
Given the provided information, there's no definitive answer here, only guesses.