I try to build a 4-bit CPU which can implement ADD(000), AND(001), OR(010), NOT(011), SLT(100), SM(101), LM(110), and LI(111), and I get the following errors:
Error: (vlog-13069) D:/modelsim/examples/cpu.v(48): near "=": syntax
error, unexpected '=', expecting ++ or --.
Error: (vlog-13069) D:/modelsim/examples/cpu.v(53): near "3": syntax
error, unexpected INTEGER NUMBER.
Error: (vlog-13069) D:/modelsim/examples/cpu.v(56): near "and": syntax
error, unexpected and.
How can I fix it?
The following is my Verilog code:
module cpu(instruction, register0, register1, register2, register3,
memory0, memory1, memory2, memory3, memory4, memory5, memory6, memory7,
memory8, memory9, memory10, memory11, memory12, memory13, memory14, memory15, overflow);
input [8:0] instruction;
output [3:0] register0; output [3:0] register1; output [3:0] register2; output [3:0] register3;
output [3:0] memory0; output [3:0] memory1; output [3:0] memory2; output [3:0] memory3;
output [3:0] memory4; output [3:0] memory5; output [3:0] memory6; output [3:0] memory7;
output [3:0] memory8; output [3:0] memory9; output [3:0] memory10; output [3:0] memory11;
output [3:0] memory12; output [3:0] memory13; output [3:0] memory14; output [3:0] memory15;
output overflow;
//there are 8 kinds of op code for u to choose.
//u can save four nums in register, or save 16 nums in memory. there's also a num for u to check it's overflow or not
reg overflow;
reg [3:0] register [3:0];
reg [3:0] memory [15:0];
reg [1:0] rs, rt, rd;
reg [2:0] op;
//create four 4-bits registers, and sixteen 4-bits memories.
//rs, rt, rd are the addresses of the register or memory
reg [3:0] c, a, b, address;
reg [4:0] sum;
//a, b used to calculate the num stored in register or memory
//address is the address of memory
//for checking out the overflowing, we need 'sum' to be 5-bits
integer i;
initial
begin
for (i = 0; i < 4; i = i + 1)
register [i] = 4'b0000;
for (i = 0; i < 16; i = i + 1)
memory[i] = 4'b0000;
end
//initialize all the register and memory
//your code~
always#(*)begin
op = instruction[8:6];
rs = instruction[5:4];
rt = instruction[3:2];
rd = instruction[1:0];
case(op)
3'b000:
a = register[rs];
b = register[rt];
sum = a + b;
overflow = sum[4];//if overflow is 1, then it does.
register[rd] = sum;
3'b001:
a = register[rs];
b = register[rt];
and f0(c[0], a[0], b[0]);
and f1(c[1], a[1], b[1]);
and f2(c[2], a[2], b[2]);
and f3(c[3], a[3], b[3]);
register[rd] = c;
3'b010:
a = register[rs];
b = register[rt];
or f0(c[0], a[0], b[0]);
or f1(c[1], a[1], b[1]);
or f2(c[2], a[2], b[2]);
or f3(c[3], a[3], b[3]);
register[rd] = c;
3'b011:
a = register[rs];
b = register[rt];
not f0(c[0], a[0], b[0]);
not f1(c[1], a[1], b[1]);
not f2(c[2], a[2], b[2]);
not f3(c[3], a[3], b[3]);
register[rd] = c;
3'b100:
a = register[rs];
b = register[rt];
if(a < b) begin
register[rd] = 4'b0001;end
else begin
register[rd] = 4'b0000;end
3'b101:
address = instruction[3:0];
memory[address] = register[rs];//can i really write like this?
3'b110:
address = instruction[5:2];
register[rd] = memory[address];//can i really write like this?
3'b111:
a = instruction[5:2];
register[rd] = a;
endcase
end
assign register0 = register[0]; assign register1 = register[1];
assign register2 = register[2]; assign register3 = register[3];
assign memory0 = memory[0]; assign memory1 = memory[1];
assign memory2 = memory[2]; assign memory3 = memory[3];
assign memory4 = memory[4]; assign memory5 = memory[5];
assign memory6 = memory[6]; assign memory7 = memory[7];
assign memory8 = memory[8]; assign memory9 = memory[9];
assign memory10 = memory[10]; assign memory11 = memory[11];
assign memory12 = memory[12]; assign memory13 = memory[13];
assign memory14 = memory[14]; assign memory15 = memory[15];
endmodule
Multiple lines in a case statement branch must be enclosed between begin and end, eg
3'b000:
begin
a = register[rs];
b = register[rt];
sum = a + b;
overflow = sum[4];//if overflow is 1, then it does.
register[rd] = sum;
end
Related
I created a microsystem which is composed of two clocked SRAMs, one designed for storing instruction-codes, and another to store some output values. The instruction SRAM has an interface module, named "user" which provides a mechanism to ease the writing process, consequently, when writing data in the memory, there is no need to specify the corresponding memory address at which those instructions have to be stored. Similarly, when reading data from the second SRAM, there is no need to specify the corresponding memory address from which data is extracted, thanks to "display" module. To be more specific, when writing data in the instructions memory, a counter increments the address pointer after each writing, while the second memory has another counter which increments the address pointer value after each reading. When one tries to read information from the instruction memory, they have to specify the memory address from which data should be read, and, as expected, when one tries to write information in the output memory, they have to specify the memory address in which data should be written. Furthermore, the microsystem has an automaton which takes input data from the instruction memory and processes it. After processing information, the automaton stores some output values in the output memory. I come across an issue when simulating, because, apparently, the read values from the SRAM memory cannot be seen, namely, rd_data_instrucions, thus, neither the input values "in" for the automaton cannot be found, nor the output values, as long as they depend on the data read from the first SRAM. I posted the code below and a diagram.
//wishbone module
module wishbone(
input clk,rst,
output reg [2:0]in,
output reg wr_en_instructions,wr_en_display,
input [2:0] wr_data_instructions,//created for usr, in order to make possible to write data
output reg [3:0] wr_data_display,
output [2:0] rd_data_instructions,
output [3:0] rd_data_display,//created for user, in order to make possible the display
output [12:0]o
);
reg [15:0] pointer_instructions,pointer_display;
initial wr_en_instructions = 1'b1;//?
control_unit i0(.clk(clk),.rst(rst),.in(in),.o(o));
user i1(.clk(clk),.wr_en(wr_en_instructions),.address_in(pointer_instructions),.wr_data(wr_data_instructions),.rd_data(rd_data_instructions));
display i2(.clk(clk),.wr_en(wr_en_display),.address_in(pointer_display),.wr_data(wr_data_display),.rd_data(rd_data_display));
integer i = 0;
always # * begin
wr_en_display = ~wr_en_instructions;
end
always #(posedge clk) begin
if(rst) begin
wr_en_instructions <= 1'b1;
pointer_instructions <= 16'd0;
pointer_display <= 16'd0;
end
else begin
if(wr_en_instructions) begin
if(wr_data_instructions[2] == 1'b1) begin
pointer_instructions <= 16'd0;
pointer_display <= 16'd0;
wr_en_instructions <= 1'b0;
end
end
else begin
in <= rd_data_instructions;
pointer_instructions <= pointer_instructions + 1;
if(rd_data_instructions == 3'b010) begin
wr_data_display <= o;
pointer_display <= pointer_display + 1;
end
else if(rd_data_instructions == 3'b100) begin
wr_en_instructions <= 1'b1;
end
end
end
end
endmodule
//testbench for top module
module wishbone_tb(
output reg clk,rst,
output [2:0]in,
output wr_en_instructions,wr_en_display,
output reg [2:0] wr_data_instructions,//created for usr, in order to make possible to write data
output [3:0] wr_data_display,
output [2:0] rd_data_instructions,
output [3:0] rd_data_display,//created for user, in order to make possible the display
output [12:0]o
);
wishbone cut(
.clk(clk),.rst(rst),
.in(in),
.wr_en_instructions(wr_en_instructions),.wr_en_display(wr_en_display),
.wr_data_instructions(wr_data_instructions),
.wr_data_display(wr_data_display),
.rd_data_instructions(rd_data_instructions),
.rd_data_display(rd_data_display),
.o(o)
);
initial $dumpvars(0,wishbone_tb);
initial begin
clk = 1'b1;
repeat (600000)
#100 clk = ~clk;
end
initial begin
rst = 1'b1;
#400 rst = 1'b0;
end
initial begin
wr_data_instructions = 3'd1;
#3000400 wr_data_instructions = 3'd2;
#1000000 wr_data_instructions = 3'd1;
#3000000 wr_data_instructions = 3'd0;
#2000000 wr_data_instructions = 3'd3;
#1000000 wr_data_instructions = 3'd1;
#3000000 wr_data_instructions = 3'd4;//halt
end
endmodule
//code for the first memory:
//stores instructions
module sram_1port_instructions(
input clk,//clocked memory
input wr_en,//when high, data is writeen, otherwise is read
input [15:0] address_in,//suppose timer cannot count more than 13ms
input [2:0] wr_data,//3 bit instructions
output reg [2:0] rd_data
);
reg [2:0] memory [2 ** 15 - 1 : 0];
always #(posedge clk) begin
if(wr_en) memory[address_in] <= wr_data;
else rd_data <= memory[address_in];
end
endmodule
//user interface designed for the first memory
module user(
input clk,
input wr_en,
input [15:0] address_in,
input [2:0] wr_data,
output [2:0] rd_data
);
reg [15:0] pointer,address;
initial pointer = 16'd0;
sram_1port_instructions i0(.clk(clk),.wr_en(wr_en),.address_in(address),.wr_data(wr_data),.rd_data(rd_data));
always #(posedge clk) begin
if(wr_en) begin
address <= pointer;
pointer <= pointer + 1;
end
else begin
address <= address_in;
pointer <= 16'd0;
end
end
endmodule
//user tb
module user_tb(
output reg clk, wr_en,
output reg [15:0] address_in,
output reg [2:0] wr_data,
output [2:0] rd_data
);
user cut(.clk(clk),.wr_en(wr_en),.address_in(address_in),.wr_data(wr_data),.rd_data(rd_data));
initial $dumpvars(0,user_tb);
initial begin
clk = 1'd1;
repeat (2000)
#100 clk = ~clk;
end
initial begin
wr_en = 1'd1;
#100000 wr_en = 1'd0;
end
integer i;
initial begin
wr_data = 3'd0;
for(i = 1;i < 500;i = i + 1) begin
#200 wr_data = i;
end
end
initial begin
address_in = 16'd0;
#100000 address_in = 16'd0;
for(i = 1;i < 500;i = i + 1) begin
#200 address_in = i;
end
end
endmodule
//code for the second memory:
//stores output data
module sram_1port_data(
input clk,//clocked memory
input wr_en,//when high, data is written, otherwise is read
input [15:0] address_in,//suppose timer cannout count more than 13ms
input [3:0] wr_data,//memory does not sotre values greater than 13(ms)
output reg [3:0] rd_data
);
reg [3:0] memory [2 ** 15 - 1 : 0];
always #(posedge clk) begin
if(wr_en) memory[address_in] <= wr_data;
else rd_data <= memory[address_in];
end
endmodule
//display interfacedesigned for the second memory
module display(
input clk,
input wr_en,
input [15:0] address_in,
input [3:0] wr_data,
output [3:0] rd_data
);
reg [15:0] pointer,address;
initial pointer = 16'd0;
sram_1port_data i0(.clk(clk),.wr_en(wr_en),.address_in(address),.wr_data(wr_data),.rd_data(rd_data));
always #(posedge clk) begin
if(!wr_en) begin
address <= pointer;
pointer <= pointer + 1;
end
else begin
address <= address_in;
pointer <= 16'd0;
end
end
endmodule
//tb for display
module display_tb(
output reg clk,
output reg wr_en,
output reg [15:0] address_in,
output reg [3:0] wr_data,
output [3:0] rd_data
);
display i0(.clk(clk),.wr_en(wr_en),.address_in(address_in),.wr_data(wr_data),.rd_data(rd_data));
initial $dumpvars(0,display_tb);
initial begin
clk = 1'd1;
repeat (2000)
#100 clk = ~clk;
end
initial begin
wr_en = 1'd1;
#100000 wr_en = 1'd0;
end
integer i;
initial begin
wr_data = 3'd0;
address_in = 16'd0;
for(i = 1;i < 500;i = i + 1) begin
#200;
wr_data = i;
address_in = i;
end
end
endmodule
//code for the control unit:
//control unit
module control_unit(
input clk,rst,
input [2:0]in,
output [12:0]o
);
wire f,g;
automaton i0(.clk(clk),.rst(rst),.in(in),.clr(f),.en(g));
circuit i1(.clk(clk),.clr(f),.en(g),.o(o));
endmodule
//code for automaton:
//atuomaton
module automaton(
input clk,rst,
input [2:0]in,
output reg clr,en
);
localparam S0_ST = 2'b00;
localparam S1_ST = 2'b01;
localparam S2_ST = 2'b10;
reg [1:0] st_reg,st_nxt;
always # * begin
case(st_reg)
S0_ST: if(!in[1]) st_nxt = S0_ST;
else if(in[0]) st_nxt = S2_ST;
else st_nxt = S1_ST;
S1_ST: if(!in[0]) st_nxt = S1_ST;
else if(in[1]) st_nxt = S2_ST;
else st_nxt = S0_ST;
S2_ST: if(in == 2'd1) st_nxt = S0_ST;
else st_nxt = S2_ST;
endcase
end
always # * begin
case(st_reg)
S0_ST: {clr,en} = 2'd1;
S1_ST: {clr,en} = 2'd0;
S2_ST: clr = 1'd1;
endcase
end
always #(posedge clk) begin
if(rst) st_reg <= S2_ST;
else st_reg <= st_nxt;
end
endmodule
//code for circuit:
//circuit
module circuit(
input clk,clr,en,
output [12:0] o
);
wire f;
generator i0(.clk(clk),.clr(clr),.en(en),.o(f));
counter i1(.clk(clk),.clr(clr),.en(f),.o(o));
endmodule
//code for counter:
//counter
module counter(
input clk,clr,en,
output reg [12:0] o
);
reg [12:0] st_nxt;
always # (posedge clk) begin
if(clr) o <= 13'd0;
else o <= st_nxt;
end
always # *
if(en) st_nxt = o + 1;
else st_nxt = o;
endmodule
//code for generator:
//pulse generator
module generator(
input clk,clr,en,
output reg o
);
reg [12:0] st_reg,st_nxt;
always #(posedge clk) begin
if(clr) st_reg <= 13'd0;
else st_reg <= st_nxt;
end
always # * begin
if(en) begin
if(st_reg == 13'd4999) begin
st_nxt = 13'd0;
o = 1'b1;
end
else begin
st_nxt = st_reg + 1;
o = 1'b0;
end
end
else begin
if(st_reg == 13'd4999) begin
st_nxt = 13'd0;
o = 1'b0;
end
else begin
st_nxt = st_reg;
o = 1'b0;
end
end
end
endmodule
When you read from address 0x8001, that is beyond the limit of your memory size. You could increase your memory. Change:
reg [2:0] memory [2 ** 15 - 1 : 0];
to:
reg [2:0] memory [2 ** 16 - 1 : 0];
This gets rid of the unknown (X) when you read from address 0x8001.
Or, if you don't want to enlarge the memory, make sure you limit your addresses.
I have a question related to the implementation of a clocked SRAM memory which is is supposed to store data written by user and then display the memory content. In addition, I created a module named display which eases the reading process so that there is no need to provide the memory address from which data should be extracted, by incrementing a register after each reading. Nevertheless, when I simulate the circuit, I cannot see the correct output; thus, when I read the memory, I notice some undefined output sequences. I posted the corresponding code below.
//stores output data
module sram_1port_data(
input clk,//clocked memory
input wr_en,//when high, data is written, otherwise is read
input [15:0] address_in,//suppose timer cannout count more than 13ms
input [3:0] wr_data,//memory does not sotre values greater than 13(ms)
output reg [3:0] rd_data
);
reg [3:0] memory [2 ** 15 - 1 : 0];
always #(posedge clk) begin
if(wr_en) memory[address_in] <= wr_data;
else rd_data <= memory[address_in];
end
endmodule
//display interfacedesigned for the second memory
module display(
input clk,
input wr_en,
input [15:0] address_in,
input [3:0] wr_data,
output [3:0] rd_data
);
reg [15:0] pointer,address;
initial pointer = 16'd0;
sram_1port_data i0(.clk(clk),.wr_en(wr_en),.address_in(address),.wr_data(wr_data),.rd_data(rd_data));
always #(posedge clk) begin
if(!wr_en) begin
address <= pointer;
pointer <= pointer + 1;
end
else address <= address_in;
end
endmodule
//tb for display
module display_tb(
output reg clk,
output reg wr_en,
output reg [15:0] address_in,
output reg [3:0] wr_data,
output [3:0] rd_data
);
display i0(.clk(clk),.wr_en(wr_en),.address_in(address_in),.wr_data(wr_data),.rd_data(rd_data));
initial $dumpvars(0,display_tb);
initial begin
clk = 1'd1;
repeat (2000)
#100 clk = ~clk;
end
initial begin
wr_en = 1'd1;
#100000 wr_en = 1'd0;
end
integer i;
initial begin
wr_data = 3'd0;
for(i = 1;i < 500;i = i + 1) begin
#200 wr_data = i;
end
end
initial begin
address_in = 16'd0;
for(i = 1;i < 500;i = i + 1) begin
#200 address_in = i;
end
end
endmodule
When I look at waveforms, I see that rd_data is unknown (X) on every other read. Looking at an internal address signal, I see that the unknowns are only for even addresses. Early in the simulation, you are only writing to even addresses.
In your testbench, you are using the same variable (i) in 2 different for loops. In your 2nd for loop, use a different variable name (j, for example):
integer j;
initial begin
address_in = 16'd0;
for(j = 1;j < 500;j = j + 1) begin
#200 address_in = j;
end
end
Now, all reads have known values because it writes to all addresses (even and odd).
You could also set the address inside the same for loop as the write data. This is likely a better approach in this case.
initial begin
wr_data = 3'd0;
address_in = 16'd0;
for(i = 1;i < 500;i = i + 1) begin
#200;
wr_data = i;
address_in = i;
end
end
I have a question related to a Verilog implementation of an SRAM memory. Module sram_1port is supposed to be a clocked address addressable SRAM memory which has a read enable signal and a write enable signal. Module control_sram is supposed to read/write data in SRAM. Data is stored contiguously, at consecutive memory addresses. The issue occurs when I try to simulate the circuit behaviour, thus the rd_data signal is undetermined during the whole simulation. So, the memory content couldn't be output, and I don't even know why. Is there a problem when data is stored, or when the content should be output, or both are problematic?
module sram_1port(
input clk,
input [15:0] address,
input wr,rd,
input [2:0] wr_data,
output reg [2:0] rd_data
);
reg [2:0] mem_reg [15:0];
always # (posedge clk) begin
if(wr) mem_reg[address] <= wr_data;
else if(rd) rd_data <= mem_reg[address];
end
endmodule
//automaton
module control_sram(
input clk, wr, rd,
input [2:0] wr_data,//read 1 instruction/clk
output [2:0] rd_data,//output
output reg [15:0] out//outputs address
);
reg [15:0] address,address_rd,address_wr;
initial address = 16'd0;
initial address_wr = 16'd0;
initial address_rd = 16'd0;
sram_1port i0(.clk(clk),.address(address),.wr(wr),
.rd(rd),.wr_data(wr_data),.rd_data(rd_data));
always #(posedge clk) begin
if(wr) begin
address_wr = address_wr + 1;
address = address_wr;
address_rd = 16'd0;
end
else if(rd) begin
address_rd = address_rd + 1;
address = address_rd;
address_wr = 16'd0;
end
end
always # * out = address;
endmodule
//tb for control_sram
module control_sram_tb(
output reg clk,wr,rd,
output reg [2:0] wr_data,
output [2:0] rd_data,
output [15:0] out
);
control_sram cut(.clk(clk),.wr(wr),.rd(rd),.wr_data(wr_data),
.rd_data(rd_data),.out(out));
initial $dumpvars(0,control_sram_tb);
initial begin
clk = 1'd1;
repeat (260000)
#100 clk = ~clk;
end
initial begin
wr_data = 3'd1;
#3000000 wr_data = 3'd2;
#1000000 wr_data = 3'd1;
#3000000 wr_data = 3'd0;
#2000000 wr_data = 3'd3;
#1000000 wr_data = 3'd1;
end
initial begin
rd = 1'b0;
#13000000 rd = 1'b1;
end
initial begin
wr = 1'b1;
#13000000 wr = 1'b0;
end
endmodule
When I run your simulation, I see rd_data go from X to 1 at time 13_000_200ns, and it stays at 1 for 3_000ns, then it returns to X. You should see that if you zoom in on your waveforms to that time interval. If you don't see that with icarus, run your simulation on edaplayground with different simulators.
Also, you declared your memory (mem_reg) to have 16 locations ([15:0]). However, I see your address take on the values of 17, 18, 19, etc. for your writes and reads. It seems strange that you are trying to access locations that are not in your memory. When you do this for reads, you get X (as expected). It seems like you only need a 4-bit address, not a 16-bit address.
I am supposed to create 4 bit full adder verilog code in vivado.But when I try to test in the simulation.It give me z and x output.Which part of code I have to change to get an output in simulation
module my_full_adder( input A,
input B,
input CIN,
output S,
output COUT
);
assign S = A^B^CIN;
assign COUT = (A&B) | (CIN&(A^B));
endmodule
This is the one bit full adder verilog code
I have check the schematic for this code and everything is correct.
module four_bit_adder(
input [3:0] A,
input [3:0] B,
input C0,
output [3:0] S,
output C4
);
wire C1,C2,C3;
my_full_adder fa0 (A[0],B[0],C0,S[0],C1);
my_full_adder fa1 (A[1],B[1],C1,S[1],C2);
my_full_adder fa2 (A[2],B[2],C2,S[2],C3);
my_full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule
Test bench
module test_4_bit(
);
reg [3:0] A;
reg [3:0] B;
reg C0;
wire [3:0] S;
wire C4;
four_bit_adder dut(A,B,C0,S,C4);
initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
end
endmodule
I don't have any idea about your testbench code but I think you have a mistake in your main code.Please try again with this code:
module fourbit_fulladder(Sum ,Cout , Cin , X ,Y);
output [3:0]Sum;
output Cout;
input Cin;
input [3:0]X,Y;
wire C1,C2,C3;
FullAdder_m FA1(Sum[0],C1,X[0],Y[0],Cin);
FullAdder_m FA2(Sum[1],C2,X[1],Y[1],C1);
FullAdder_m FA3(.S(Sum[2]),.Cout(C3),.A(X[2]),.B(Y[2]),.Cin(C2));
FullAdder_m FA4(.S(Sum[3]),.Cout(Cout),.A(X[3]),.B(Y[3]),.Cin(C3));
endmodule
enter code here
module fulladder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);
/*assign cin=0;*/
wire c1,c2,c3;
adder fa0 (a[0],b[0],cin,sum[0],c1);
adder fa1 (a[1],b[1],c1,sum[1],c2);
adder fa2 (a[2],b[2],c2,sum[2],c3);
adder fa3 (a[3],b[3],c3,sum[3],cout);
endmodule
first design full adder to implemet the above
module adder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = (a&b) | (cin&(a^b));
endmodule
ucf file
NET "a[0]" LOC = "A10";
NET "a[1]" LOC = "D14";
NET "a[2]" LOC = "C14";
NET "a[3]" LOC = "P15";
NET "b[0]" LOC = "P12";
NET "b[1]" LOC = "R5";
NET "b[2]" LOC = "T5";
NET "b[3]" LOC = "E4";
NET "sum[0]" LOC = "U18";
NET "sum[1]" LOC = "M14";
NET "sum[2]" LOC = "N14";
NET "sum[3]" LOC = "L14";
NET "cout" LOC = "M13";
The above ucf file is for Spartan 6 board
module testing123(Clk, Rst_n);
. . .
wire [7:0] port1_data;
wire [7:0] port2_data;
wire [7:0] port3_data;
wire [7:0] port4_data;
wire [7:0] port5_data;
wire [7:0] port6_data;
wire [7:0] port7_data;
wire [7:0] port8_data;
wire [7:0] port9_data;
wire [7:0] port10_data;
wire [7:0] port11_data;
wire [7:0] port12_data;
wire [7:0] port13_data;
wire [7:0] port14_data;
wire [7:0] port15_data;
reg [flit_port_width-1:0] flit_out1;
reg [flit_port_width-1:0] flit_out2;
reg [flit_port_width-1:0] flit_out3;
reg [flit_port_width-1:0] flit_out4;
reg [flit_port_width-1:0] flit_out5;
reg [flit_port_width-1:0] flit_out6;
reg [flit_port_width-1:0] flit_out7;
reg [flit_port_width-1:0] flit_out8;
reg [flit_port_width-1:0] flit_out9;
reg [flit_port_width-1:0] flit_out10;
reg [flit_port_width-1:0] flit_out11;
reg [flit_port_width-1:0] flit_out12;
reg [flit_port_width-1:0] flit_out13;
reg [flit_port_width-1:0] flit_out14;
reg [flit_port_width-1:0] flit_out15;
. . .
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory1(.clk(Clk)
,.rst(Rst_n)
,.flit_out(flit_out1)
,.dataout(port1_data)
);
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory2(.clk(Clk)
,.rst(Rst_n)
,.flit_out(flit_out2)
,.dataout(port2_data)
);
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory3(.clk(Clk) ...
);
. . .
endmodule
module RAM_Memory(
flit_out,
rst,
clk,
dataout
);
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
integer count, i;
input [34:0] flit_out;
input rst,clk;
output [data_width - 1 : 0] dataout;
reg we;
reg [data_width - 1 : 0] dataout;
reg [addr_width - 1 : 0] addr;
reg [data_width - 1 : 0] data_in;
reg [data_width - 1 : 0] mem [lo:hi];
initial begin
count =0; i=0;
end
always #(posedge clk)begin
count<=count+1;
we<=0;
if(count>=1) begin
we<=1;
end
end
always #(we)begin
assign data_in = flit_out[7:0];
assign addr = flit_out[23:8];
mem[addr]<= data_in;
assign dataout = mem[addr];
end
always #(count)begin
if(count>=68)begin
count<=0;
end
end
endmodule
Here, one RAM_Memory module is given which is use in to other module testing123 by port mapping for storing data to 64 wide memory from 15 ports. But only one port memory module store 64 datas, "mem" register is not refreshing for others mapping module. Data will be loss. How to refresh the "mem" register or start from 0 value for all mapping port?
Accessing instance of one module from inside of several other modules? (verilog)
I do not fully understand the question but have spotted some errors. Your code contains :
always #(we)begin
assign data_in = flit_out[7:0];
assign addr = flit_out[23:8];
mem[addr]<= data_in;
assign dataout = mem[addr];
end
Which contains a few issues.
Your triggering the always on we but not using we inside the block. This does not represent anything in hardware. It is more likely that you want a flipflop to update when enable is high.
code example
always #(posedge clk) begin
if (en) begin
//..
end
end
Using assign inside always probably does not do what you expect.
You most likely just want :
always #* begin
data_in = filt_out[7:0]
addr = flit_out[23:8];
dataout = mem[addr];
It is best practice not to mix non-blocking (<=) and blocking (=) assignments. If they are all meant to be flipflops (#(posedge clk)) then use non-blocking (<=) if it is combinatorial (always #*) then use blocking (=).
The block of code in question would become
always #(posedge clk)begin
if (we) begin
data_in <= flit_out[7:0];
addr <= flit_out[23:8];
mem[addr] <= data_in;
dataout <= mem[addr];
end
end
Looking at the code I expect that is not what you want data_in and addr decoding should be done outside of this block.
//Semantically split the bus
assign data_in = flit_out[7:0];
assign addr = flit_out[23:8];
always #(posedge clk)begin
if (we) begin
mem[addr] <= data_in;
dataout <= mem[addr];
end
end
Some recommendations to make reading your code easier.
Using modern port declarations makes a big difference to readability.
module RAM_Memory(
flit_out,
rst,
clk,
dataout
);
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input [34:0] flit_out;
input rst,clk;
output [data_width - 1 : 0] dataout;
reg [data_width - 1 : 0] dataout;
becomes
module RAM_Memory#(
parameter ADDR_WIDTH = 1, //They don not have to be upper case
parameter DATA_WIDTH= 1, // But most languages semantically define upper case as constants
parameter LO = 0;
parameter HI = 1;
)(
input [34:0] flit_out,
input rst,
input clk,
output [DATA_WIDTH-1:0] dataout
);
Your instance can move from :
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory2(.clk(Clk)
,.rst(Rst_n)
,.flit_out(flit_out2)
,.dataout(port2_data)
);
to
RAM_Memory #(
.ADDR_WIDTH( 6 ), //No need to specify the width of parameter
.DATA_WIDTH( 8 ),
.LO ( 0 ),
.HI ( 63 )
) Memory2 (
.clk ( Clk )
,.rst ( Rst_n )
,.flit_out ( flit_out2 )
,.dataout ( port2_data)
);