how to map memory for 16 ports in verilog - memory

Question

module testing123(Clk, Rst_n);
. . .
wire [7:0] port1_data;
wire [7:0] port2_data;
wire [7:0] port3_data;
wire [7:0] port4_data;
wire [7:0] port5_data;
wire [7:0] port6_data;
wire [7:0] port7_data;
wire [7:0] port8_data;
wire [7:0] port9_data;
wire [7:0] port10_data;
wire [7:0] port11_data;
wire [7:0] port12_data;
wire [7:0] port13_data;
wire [7:0] port14_data;
wire [7:0] port15_data;
reg [flit_port_width-1:0] flit_out1;
reg [flit_port_width-1:0] flit_out2;
reg [flit_port_width-1:0] flit_out3;
reg [flit_port_width-1:0] flit_out4;
reg [flit_port_width-1:0] flit_out5;
reg [flit_port_width-1:0] flit_out6;
reg [flit_port_width-1:0] flit_out7;
reg [flit_port_width-1:0] flit_out8;
reg [flit_port_width-1:0] flit_out9;
reg [flit_port_width-1:0] flit_out10;
reg [flit_port_width-1:0] flit_out11;
reg [flit_port_width-1:0] flit_out12;
reg [flit_port_width-1:0] flit_out13;
reg [flit_port_width-1:0] flit_out14;
reg [flit_port_width-1:0] flit_out15;
. . .
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory1(.clk(Clk)
,.rst(Rst_n)
,.flit_out(flit_out1)
,.dataout(port1_data)
);
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory2(.clk(Clk)
,.rst(Rst_n)
,.flit_out(flit_out2)
,.dataout(port2_data)
);
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory3(.clk(Clk) ...
);
. . .
endmodule
module RAM_Memory(
flit_out,
rst,
clk,
dataout
);
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
integer count, i;
input [34:0] flit_out;
input rst,clk;
output [data_width - 1 : 0] dataout;
reg we;
reg [data_width - 1 : 0] dataout;
reg [addr_width - 1 : 0] addr;
reg [data_width - 1 : 0] data_in;
reg [data_width - 1 : 0] mem [lo:hi];
initial begin
count =0; i=0;
end
always #(posedge clk)begin
count<=count+1;
we<=0;
if(count>=1) begin
we<=1;
end
end
always #(we)begin
assign data_in = flit_out[7:0];
assign addr = flit_out[23:8];
mem[addr]<= data_in;
assign dataout = mem[addr];
end
always #(count)begin
if(count>=68)begin
count<=0;
end
end
endmodule
Here, one RAM_Memory module is given which is use in to other module testing123 by port mapping for storing data to 64 wide memory from 15 ports. But only one port memory module store 64 datas, "mem" register is not refreshing for others mapping module. Data will be loss. How to refresh the "mem" register or start from 0 value for all mapping port?

Answer 1

Accessing instance of one module from inside of several other modules? (verilog)

Answer 2

I do not fully understand the question but have spotted some errors. Your code contains :
always #(we)begin
assign data_in = flit_out[7:0];
assign addr = flit_out[23:8];
mem[addr]<= data_in;
assign dataout = mem[addr];
end
Which contains a few issues.
Your triggering the always on we but not using we inside the block. This does not represent anything in hardware. It is more likely that you want a flipflop to update when enable is high.
code example
always #(posedge clk) begin
if (en) begin
//..
end
end
Using assign inside always probably does not do what you expect.
You most likely just want :
always #* begin
data_in = filt_out[7:0]
addr = flit_out[23:8];
dataout = mem[addr];
It is best practice not to mix non-blocking (<=) and blocking (=) assignments. If they are all meant to be flipflops (#(posedge clk)) then use non-blocking (<=) if it is combinatorial (always #*) then use blocking (=).
The block of code in question would become
always #(posedge clk)begin
if (we) begin
data_in <= flit_out[7:0];
addr <= flit_out[23:8];
mem[addr] <= data_in;
dataout <= mem[addr];
end
end
Looking at the code I expect that is not what you want data_in and addr decoding should be done outside of this block.
//Semantically split the bus
assign data_in = flit_out[7:0];
assign addr = flit_out[23:8];
always #(posedge clk)begin
if (we) begin
mem[addr] <= data_in;
dataout <= mem[addr];
end
end
Some recommendations to make reading your code easier.
Using modern port declarations makes a big difference to readability.
module RAM_Memory(
flit_out,
rst,
clk,
dataout
);
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input [34:0] flit_out;
input rst,clk;
output [data_width - 1 : 0] dataout;
reg [data_width - 1 : 0] dataout;
becomes
module RAM_Memory#(
parameter ADDR_WIDTH = 1, //They don not have to be upper case
parameter DATA_WIDTH= 1, // But most languages semantically define upper case as constants
parameter LO = 0;
parameter HI = 1;
)(
input [34:0] flit_out,
input rst,
input clk,
output [DATA_WIDTH-1:0] dataout
);
Your instance can move from :
RAM_Memory #(/*addr_width*/ 32'd16,
/*data_width*/ 32'd8,
/*lo*/ 32'd0,
/*hi*/ 32'd63) Memory2(.clk(Clk)
,.rst(Rst_n)
,.flit_out(flit_out2)
,.dataout(port2_data)
);
to
RAM_Memory #(
.ADDR_WIDTH( 6 ), //No need to specify the width of parameter
.DATA_WIDTH( 8 ),
.LO ( 0 ),
.HI ( 63 )
) Memory2 (
.clk ( Clk )
,.rst ( Rst_n )
,.flit_out ( flit_out2 )
,.dataout ( port2_data)
);