foreach & silencer in a makefile target - foreach

Question

I am using a foreach in a makefile for a particular target.
my_Target:
$(foreach x,$(MY_TARGET_DIRS), #echo " BUILD $(x)";$(Q)$(MAKE) --directory=$(x) LIB_DIR=$(MY_LIB_DIR) $(MY_TARGET_RULES); )
This is intended call the makefiles contained every specified directory of MY_TARGET_DIRS, after a string has been printed to tell which build is ongoing.
The Q variable is defined as follows:
# Silent per default, 'make V=1' shows all compiler calls.
ifneq ($(V),1)
Q := #
endif
So that the make command is verbose if V=1 is defined.
For V=1 the output log is:
make my_Target V=1
BUILD /dir1
make[1]: Entering directory `/dir1'
make[1]: Nothing to be done for `elf'.
make[1]: Nothing to be done for `bin'.
make[1]: Leaving directory `/dir1'
/bin/sh: #echo: command not found
make[1]: Entering directory `/dir2'
make[1]: Nothing to be done for `elf'.
make[1]: Nothing to be done for `bin'.
make[1]: Leaving directory `/dir2'
While if I do not define V=1, the output log is:
make my_Target
BUILD /dir1
/bin/sh: #make: command not found
/bin/sh: #echo: command not found
/bin/sh: #make: command not found
make: *** [my_Target] Error 127
How can I get the behavior I desire correctly?
Bye!

Answer 1

Put the # ($(Q)) at the beginning of the recipe:
my_Target:
$(Q)$(foreach x,$(MY_TARGET_DIRS), echo " BUILD $(x)";$(MAKE) --directory=$(x) LIB_DIR=$(MY_LIB_DIR) $(MY_TARGET_RULES); )
Notice that the foreach will ouptut a single recipe line, and the # will apply to all of it. An alternative, if you want to get more fancy is to create a rule for each of the target dirs:
MY_TARGET_DIRS_TARGS=$(MY_TARGET_DIRS:%=%/.phony)
my_Target: $(MY_TARGET_DIRS_TARG)
$(MY_TARGET_DIRS_TARGS):
#echo " BUILD $(x)"
$(Q)(MAKE) --directory=$(x) LIB_DIR=$(MY_LIB_DIR) $(MY_TARGET_RULES);
.PHONY: $(MY_TARGET_DIRS_TARGS)