What is allowed and what not in terms of alignment for emscripten?
I guess an int should have an address with the lower 2 bits == 0.
How about a char? Should it also have the lower two bits == 0 for it's address? or can it be at all addresses?
How about a double or int64_t? Are the lowest two bits == 0 enough or should it be the lowest 3 bits == 0 ?
A friend of mine just told me:
The requirement is to follow standard C alignment rule for types. Which says that each type should be aligned at an address that is a multiple of the size of the type in question.
https://en.wikipedia.org/wiki/Data_structure_alignment#Typical_alignment_of_C_structs_on_x86
floats are always stored as 32 bit floats in emscripten. -s PRECISE_FP32=0 or 2 just does the calculations in 64 bits but storage is still done as 32 bit floats.
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I'm reading this book 3 easy pieces by remzi. In chapter 18 paging introduction in the first paragraph it is written
(real address spaces are much bigger, of course,
commonly 32 bits and thus 4-GB of address space, or even 64 bits)
Now if 1 byte is 8 bits, shouldn't 32 bits be 32/8 4 bytes space? I have seen the math for getting the answer as 4GB
2^10 = 1KB
2^10 = 1MB
2^10 = 1GB
But then this is assuming 2^1 = 1B, But isn't this simply wrong?
What am I missing? What does my answer (4Bytes) represent here?
This question is related How many bits are needed to address this much memory?
But doesn't address why my math is incorrect. (OP there also has the exact same confusion).
Lets say that I change the word size to 64MB (wild I know). Then number of words is 1. According to the answers, number of bits would be 2^0 = 1, 0 bits? Then where and when do we use the fact that 1 byte = 8 bits?
Any help would be appreciated.
Today, RAM is byte addressable. Each address put on the address bus returns 1 byte. If you have 32 bits, the amount of different addresses that you can come up with is 2^32 = 4,294,967,296. Since you can have that much different addresses, then you can address that much bytes. In terms of bytes, this amount of bytes is called 4 GB.
To detect a number of n_errors errors in a code of n_total bits length, we must sacrifice a certain number n_check of the bits for some sort of checksum.
My question is: What is the method, where I have to sacrifice the least number of bits n_check to detect a given number of errors n_errors in a code of n_total bits length.
If there is no general answer to this question, I would greatly appreciate some hints concerning methods for the following conditions:
n_total=32, n_errors>1and
obviously n_check should be as small as possible.
Thank you.
Link to CRC Zoo notes:
http://users.ece.cmu.edu/~koopman/crc/notes.html
If you look at the table for 3 bit crc:
http://users.ece.cmu.edu/~koopman/crc/crc3.html
You can see that the second entry, 0xb => x^3 + x + 1, has HD (Hamming Distance) 3 for 4 data bits, for a total size of 7 bits. This can detect all 2 bit error patterns (out of 7 bits), but some 3 bit patterns will fail, an obvious case where all bits should be zero would be
0 0 0 1 0 1 1 (when it should be 0 0 0 0 0 0)
This is a simple example where the number of 1 bits in the polynomial determined the maximum number of bit errors. To verify HD = 3 (2 bit errors detected) , all 21 cases of 7 bits total, 2 bits bad were checked.
If you check out 32 bit CRCs, you'll see that 0x04c11db7 (ethernet 802.3, has HD=6 (5 bit error detection) at 263 data bits => 263+32 = 295 total bits, while 0x1f4acfb13, has HD=6 at 32736 data bits => 32736+32 = 32768 total bits.
Here is a pdf article about a search for good CRCs:
https://users.ece.cmu.edu/~koopman/networks/dsn02/dsn02_koopman.pdf
Finding "good" CRCs for specific Hamming distances requires some knowledge about the process. For example, in the case of 0x1f4acfb13 with HD=6 (5 bad bit detection), there 314,728,365,660,920,250,368 possible combinations of 5 bits bad out of 32768 bits. However, 0x1f4acfb13 = 0x1f4acfb13 = 0xc85f*0x8011*0x3*0x3, and either of the 0x3 (x+1) terms will detect any odd number of error bits, which reduces the search to 4 bad bit cases. For the minimal size of a message that fails with this polynomial, the first and last bits will be bad. This reduces the searching down to just 2 of the 5 bits, which reduces the number of cases to about 536 million. Rather than calculating CRC for each bit combination, a table of CRCs can be created for each 1 bit in an otherwise all 0 bit message, and then the table entries corresponding to specific bits can be xor'ed to speed up the process. For a polynomial where it isn't the first and last bits, a table of CRC's could be generated for all 2 bit errors (assuming such a table fits in memory), then sorted, then checked for duplicate values (with sorted data, this only requires one sequential pass of the sorted table). Duplicate values would correspond to a 4 bit failure. Other situations will require different approaches, and in some cases, it's still time consuming.
I'm reading a book about assembly; Jones and Bartlett Publishers Introduction to 80x86 Assembly
The author give exercises but no answers to it. Obviously before going further, I want
to make sure that I fully understand the chapter concepts.
donc,
What is the 8-hex-digit address of the "last" byte for a PC with 32 MBytes of RAM
This is my solution:
1) convert to bits
32 MBytes = 268435456 bits
2) I subtract 8 bits to remove the last byte
268435448
3) conversion to hexadecimal
FFFFFF8
So I got FFFFFF8
Does this look a good answer?
No. For assembly programming it's very helpful to be able to do simple power-of-2 calculations in your head. 1K is 2^10. So 1M is 2^20. So 32M is 2^25 (because 2^5 = 32). So the address of the last byte is 2^25-1 (because the first byte is at 0). This is 25 bits that are all 1's (because 2^n-1 is always n 1's). In hex, this is six F's (4 bits per F) plus an additional 1, so prepending a zero to get 8 hex digits, you have 01FFFFFF.
There are two things you should think about:
For most computers (all PCs) adresses are given in bytes, not in bits.
Therefore you must calculate: 32 MByte = 33554432 Bytes, minus 1 byte = 01FFFFFF (hex) as "Gene" wrote in his answer.
In reality (if you are interested in) you must also think about the fact that there is a "gap" in the address area (from 000A0000 to 000FFFFF) of real PCs so either not all the RAM is useable or the last address of the RAM comes later. This area is used for the graphics card and the BIOS ROM.
I thinking is : 00007FFF
because: 32MB = 32*1024 = 32768
byte last have address 32767 (7FFF)
I am confused with so many terminologies that my instructor talks about such as word,byte addressing and memory location.
I was under the impression that for a 32-bit processor,
it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
The way I think now is:
The memory is like an array of buckets each of 1 byte length.
when we say byte addressing (which I guess is the most common ones), each char is 1 byte and is retrieved from the first bucket (say for example).
for int the next 4 bytes are put together in little-endian ordering to compute the Integer value.
so each memory, I see it as, 8 bits or 1 byte, which can give upto 2^8 locations, this is far less than what cpu can address.
There is some very basic mis-understanding here on my part which if some experts can explain in simple terms that a prosepective CS-major student can it in once forever.
I have read various pages including this one on word and here the unit of address resolution is given as 8b for ARM, which adds more to my confusion.
The processor uses 32 bits to store an address. With 32 bits, you can store 2^32 distinct numbers, ranging from 0 to 2^32 - 1. "Byte addressing" means that each byte in memory is individually addressable, i.e. there is an address x which points to that specific byte. Since there are 2^32 different numbers you can put into a 32-bit address, we can address up to 2^32 bytes, or 4 GB.
It sounds like the key misconception is the meaning of "byte addressing." That only means that each individual byte has its own address. Addresses themselves are still composed of multiple bytes (4, in this case, since four 8-bit bytes are taken together and interpreted as a single 32-bit number).
I was under the impression that for a 32-bit processor, it can address upto 2^32 bits, which is 4.29 X 10^9 bits (NOT BYTES).
This is typically not the case -- bit-level addressing is quite rare. Byte addressing is far more common. You could design a CPU that worked this way, though. In that case as you said, you would be able to address up to 2^32 bits = 2^29 bytes (512 MiB).
For one bit, You would have 0 or 1 and For two bits, you would have 00, 01, 10, 11. For 8 bits, you would have 2^8 which is 256 address values. Address and Data are separate terms. Address is the location and Data is the content in that location. Data width(content) is how many bits you could store in one memory cell address.(Think like an apartment with bedrooms- each apartment in a building has two bedrooms)and Data depth(address) is how many addresses you would have(In a building how many apartments you would have #1 thru #1400 etc). One bit in the CPU register can reference an individual byte in memory like one number in apartment number can reference one apartment. SIMM module RAMs had 32 bit Data width and DIMM modules have 64 bit Data width. It means in one memory address in DIMM, It stores 64 bits data. How many addresses can be multiplexed by two wires (two bit processing), you could make 4 addresses. (Each of these addresses could hold 64 bits if it is DIMM module ). 32 bit processing means, 32 wires, 2^32 address options. Even though, 64 bit processing has 64 bit registers and internal bus (wires) as 64 bit, http://www.tech-faq.com/address-bus.html, address bus max is 44 bits. means 2^44 maximum addressing can be achieved by Intel Super Server CPU Itanium 2.
I want to generate a 16 bit unsigned integer (uint16_t) which could represent following:
First 2 digits representing some version like 1, 2, 3 etc.
Next 3 digits representing another number may be 123, 345, 071 etc.
And last 11 digits representing a number T234, T566 etc.
How can we do this using objective C. I would like to parse this data later on to get these components back. Please advise.
I think you are misunderstanding just what uint16_t means. It doesn't mean a 16 digit decimal number (which would be any number between 0 and 9,999,999,999,999,999). It means an unsigned number that can be expressed using 16 bits. The range of such a value is 0 to 65535 in decimal. If you really wanted to store the numbers you are talking about you would need 52 bits. You would also be making things very difficult for yourself, since you wouldn't easily be able to extract the first two decimal digits from that 52 bit sequence; You'd have to treat the number as a decimal value then modulus 100 it, you couldn't just say it's bits 1 to 8.
There is a scheme called Binary Coded Decimal that could help you. You would take a 64 bit value (uint64_t) and you'd say that within this value the bits 1-7 are the version (which could be a value up to 127), bits 8-17 are the second number (which could be a value up to 1023) and bits 18-63 could be your third number (those 46 bits would be able to store a number up to 70,368,744,177,663.
All this is technically possible, but you are really going to be making things hard for yourself. It looks like you are storing a version, minor version and build number and most people do that using strings, not decimals