I want to ask some questions about this diagram that showing the main memory with OS and different processes : how can I compute the size of main memory in Kbytes ? and What will happen if Process B generates a logical address of 200? Will the CPU return a
physical address or error?
I'd assume the unlabeled numbers on the left are addresses in bytes; which would imply there's 2048 bytes (or 2 KiB) of something (virtual space, or physical space, or maybe even RAM if there's no devices mapped into the physical space). Of course it could just as easily be 2048 bits, or 2048 (36-bit) words, or..
If Process B tries to access logical address of 200; it might work (no security), or it might cause some kind of trap/exception because the process doesn't have permission to access the operating system's area; or it could be impossible for the process to do that (e.g. maybe the design of the CPU restricts the process to unsigned offsets from a base address of 1203).
I am confuse about memory configuration, i have below questions.
if 32-bit os maximum virtual address is 4GB, When i have 4 gb of ram for 32-bit os, What about the virtual memory size ? is it required virtual memory or we can directly use physical memory ?
In 32-bit os 12 bits are offset because page size=4k i.e 2^12 and 2^20 for page addresses
What about 64-bit os, What is offset size ? What is page size ? How it calculated.
What is PAE? If enabled how to decide size of PAE, what is maximum and minimum size of extended memory.
Q.1
Ans:-
The 32-bit processor includes a 32-bit register, which can store 2^32 and the 64-bit processor includes a 64-bit register, which can store 2^64.
A 64-bit register can theoretically 16 exabytes of memory.
For 32-bit os maximum virtual memory is 4GB, it can address only up to 4GB of physical RAM (Without PAE).
For the Linux kernel, it works on virtual memory management i.e CPU address, There are many types of addresses For example. bus address, physical address(There are other concepts to access physical memory eg. DMA and IOMMU)
The virtual memory size is the maximum virtual size of a single process.
For more details of 32-bit and 64-bit processor use link.
Q.2
Ans:-
For 64-bit OS address space is 16 exabyte RAM. and generally page size is 8K i.e 2^13 (apart from that there is the concept of hugepages and hugetlb).
64-bit currently uses 48-bit physical addresses that allow you to address up to 256 TBytes of main memory. because the page table is also a page itself and consists of page table entries. Since the number of entries in one table is limited and depends on the entry size and page size, so tables are arranged in multiple levels. There are usually 2 or 3 levels, and sometimes even 4 levels.
General calculation of 64-bit os:-
Number of entries in page table = virtual address space size/page size
= 2^(64-13) (if page size is 8K)
= 2^51 for maximum page table entries (if you are using whole 64 bits)
Page Size == Frame Size.
Q.3
Ans:-
For PAE, the page table entry expands from 32 to 36 bits. This allows more space for the physical page address, or page frame number(PFN) field, in the page table entry. In the initial implementations of PAE, the page frame number(PFN) field was expanded from 20 to 24 bits. The size of the "byte offset" from the address being translated is still 12 bits, so total physical address size increases from 32 bits to 36 bits (from 20+12 to 24+12). This increased the physical memory that is theoretically addressable by the CPU from 4 GB to 64 GB.
Maximum size of PAE is = 64GB (2^36).
For PAE in details use link
I have got an external SRAM on my STM32F43XX and I am able to use it. I can access the memory regions and test them (memtest).
However, I do not know if my FMC configurations are correct. It is hard for me to understand the relation between the datasheet of my SRAM and the STM32F4 FMC interface.
I use the STM32F4XX reference manual with the SRAM CY7C1051DV33.
Lets start with the timing (Reference page 1591, Table 256 | SRAM Datasheet Page 6):
Address Setup <------- Address Setup to Write End?
Address Hold <------- Data Hold from Address Change?
Data Setup <------- Data Setup to Write End?
Bus Turn <-------- ?
Clock divide ratio <-------- ?
Data latency <----------- ?
AccessMode <------------- ?
The frequency? of the SRAM is defined by my HCLK divided by the clock divide ratio?
So if my HCLK is 100 MHz and the clock divide is 2 I get 50 Mhz (20 ns). So my STM32F4 latency is always bigger than the latency of the SRAM (max 10 ns). So ever where the lowest allowed value would be okay?
Thank you in advance for your help!
My NORRAM INIT looks by the way like this:
init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
init.MemoryType = FMC_MEMORY_TYPE_SRAM;
init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
init.WrapMode = FMC_WRAP_MODE_DISABLE;
init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
init.WriteBurst = FMC_WRITE_BURST_DISABLE;
init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ASYNC;
address setup is on the address bus. how much time before the clock does the ram show that the address has settled (no longer changes) and/or from the prior clock. hold is how long after the clock does it stay stable.
data setup is how long before the clock is the data stable.
the ram and the microcontroller datasheets should have timing diagrams. for the clock speed you have chosen, do you meet timing and/or do you have to set some parameters to meet timing.
The question is as follow :
A microcomputer has memory locations from 00000h to FFFFFh. Each memory
location stores 1 byte. In decimal, how many bytes can the microcomputer store in its
memory? How many Kilobytes is this?
Answer:
It requires two 2Kbytes of RAM and 512 bytes
of PROM.
I try to calculate myself before reviewing the answer,and find out that it is not same,till now i still don't understand why this is the answer,anyone may give me some help??Thanks
The answer is clearly the answer to another question and not this one.
Well, 00000h to FFFFFh, this represents 100,000h memory locations, hence 100,000h bytes. 10h^5 (hex) is 16^5 (decimal).
16^5 = (2^4)^5 = 2^20 = (1024)^2 = 1 M = 1024 K.
Conclusion: this processor can address one megabyte of memory.
Obviously, less than one megabyte is installed on this microcomputer, and not all of the installed memory is RAM. But you can't deduce this from the amount of addressable memory.
Just reading some notes in a purdue lecture about OSs, and it says:
A program sees memory as an array of
bytes that goes from address 0 to 2^32-1 (0 to
4GB-1)
Why 4 GB?
Because 32 bits are able to represent numbers up to 232 − 1 = 4294967295 = 4 GiB − 1 and therefore address up to 232 individual bytes which would be 4 GiB then.
There are ways to circumvent that, though. For example using PAE even a 32-bit operating system can support more memory. Historically this has most commonly been used on servers, though. Also, the non-server Windows SKUs don't support it. By now all that is moot, though, given that 64-bit CPUs, OSes and driver support are commonplace.
Because each byte of memory has to have an address. In a 32-bit operating system, an address is 32 bits long; thus, there are 2^32 possible addresses, which means there are 2^32 bytes = 4 GB.
If you have a 4-bit system, this means the address for each byte is 4 binary digits, the probability of all your address will range from 0000 through 1111 which is 2^4 = 16 (2 because there is either 0 or 1), with four bits it's possible to create 16 different values of zeros and ones, If you have 16 different addr. each represent a byte then you can have a max of 16 bytes
4-bit system will look like this:
For a 32-bit system, your max is 2^32 = 4294967292 bytes
Everybody is saying 2^32 = 4GiB, which is right. Just in case, here is how we got there:
A 32-bit machine uses 32 bits to address memory. Each bit has a value of 0 or 1. If you have 1 bit, you have two possible addresses: 0 or 1.
A two-bit system ( pun aside ) has four possible address: 00 =0, 01=1, 10=2, 11=3. 2^2=4.
Three bits have 8 possble addresses: 000=0, 001=1, 010=2, 011=3, 100=4, 101=5, 110=6, and 111=7.
Each bit doubles the potential address space, which is why 2^n tells you how many addresses you use for a given number of bits. 2^1 = 2, 2^2 = 2*2 = 4, 2^3 = 2*2*2 = 8, etc.
By the time you get to 32 bits, you are at 4GiB.
4 GB = 2^32 bytes.
2 ^ 32 = 4 * 1024 * 1024 * 1024
That, in bytes, is the definition of 4 GB. In other words a 32-bit register as a memory pointer can address 4 GB of memory and no more.
Actually, it's not as simple as 2^32 = 4294967296 bytes. You see in x86 protected mode, with paging enabled (that is, what you get when you use any modern OS), you don't address memory locations directly, even though the paging translation mechanism is transparent for client applications.
Of a logical 32 bit memory address, when using 4K pages:
bits 22-31 refer to a page directory
bits 12-21 refer to a page table
bits 11-0 refer to an offset in the 4096 byte page
As you can see, you have 2^10 (1024) page directories, in each page directory, you have 2^10 page tables and each page is 2^12 (4096) bytes long, hence 2^32 = 4294967296 bytes. The width of the memory bus is conveniently the same as the word length of the CPU but it's not necessary to be like this at all. In fact, more modern x86 CPUs support PAE which enables addressing more than 4GB (or GiB) even in 32-bit mode.
32bits can represent numbers 0..2^32 = 0..4,294,967,296
32bits can address up to 2^32Bytes (assuming Byte-size blocks)
2^32Bytes is the max size
2^32B = 4,194,304KiB = 4,194MiB = 4GiB
Because is the amount of different memory addresses (in Bytes) that can be stored in a Word.
But, in fact, that's not always true (in most of cases it isn't), the OS can handle more physical memory than that (with PAE) and the applications can use less than 4GB of virtual memory (because part of that virtual memory is mapped to the OS, 1GB in Linux and 2GB in Windows, for example).
Another scenario where that doesn't apply is if the memory was addressed by Words instead of Bytes, then the total memory addressable would be 16GB, for example.
A CPU with 32 bit registers will need the operating system to calculate everything in chunks of 32 bits. It's a hardware requirement to which the OS must conform. Similarly, CPUs with 64 bit registers will need an operating system that reads and writes data from the RAM in chunks of 64 bits. (Every time you read data from memory, you need to read it into one of those registers - be it 32 bit, or 64 bit, or 16 bit, etc.)
A 32 bit register can store 2^32 different RAM addresses.
Each RAM address corresponds to a byte (8 bits) in modern RAMs. (The 4 GB argument is true only for those RAMs that have addresses for every byte.)
=> 2^32 = 4,294,967,296 addresses, → that corresponds to 4,294,967,296 bytes.
Now, 1 KB = 2^10 bytes or 1024 bytes (in the binary system)
Therefore, 4,294,967,296 bytes / 1024 = 4,194,304 KB
4,194,304 KB / 1024 = 4,096 MB
4,096 MB / 1024 = 4 GB
Mainly due to 32bit OS chosing to support only 2^32-1 addresses.
If the CPU has more than 32 address lines on the FSB, then the 32bit OS can choose to use a paging mechanism to access more than 4GiB. (For example Windows 2000 Advanced Server/Data Center editions on PAE supported Intel/AMD chips)
4 GB = 2^32 bytes.
But remember its max 4gb allocated by a 32 bit OS. In reality, the OS will see less e.g. after VRAM allocation.
As previously stated by other users, 32-bit Windows OSes use 32-bit words to store memory addresses.
Actually, most 32-bit chips these days use 36-bit addressing, using Intel's Physical Address Extension (PAE) model. Some operating systems support this directly (Linux, for example).
As Raymond Chen points out, in Windows a 32-bit application can allocate more than 4GB of memory, and you don't need 64-bit Windows to do it. Or even PAE.
For that matter, 64-bit chips don't support the entire 64-bit memory space. I believe they are currently limited to 42-bit space... the 36-bit space that PAE uses, plus the top 8-bit addresses,