If something is stored at 0x1001 0000 the next thing is stored at 0x1001 0004. And if I'm correct the memory pieces in a 32-bit architecture are 32 bits each. So would 0x1001 0002 point to the second half of the 32 bits?
First of all, memory addresses in MIPS architecture are not incremented by 4. MIPS uses byte addressing, so you can address any byte from memory (see e.g. lb and lbu to read a single byte, lh and lhu to read a half-word).
The fact is that if you read words which are 32 bits length (4 bytes, lw), then two consecutive words will be 4 bytes away from each other. In this case, you would add 4 to the address of the first word to get the address of the next word.
Beside this, if you read words you have to align them in multiples of 4, otherwise you will get an alignment exception.
In your example, if the first word is stored in 0x10010000 then the next word will be in 0x10010004 and of course the first half/second half would be in 0x1001000 and 0x1001002 (the ordering will depend on the endianness of the architecture).
You seem to have answered this one yourself! 32 bits make 4 bytes, so if you're e.g. pushing to a stack, where all elements are pushed as the same size, each next item will be 4 bytes ahead (or before) the next.
Related
Let's say a computer can hold a word size of 26 bits, I'm curious to know how many memory addresses can the processor generate?
I'm thinking that the maximum number it can hold would be 2^26 - 1 and can have 2^26 unique memory addresses.
I'm also curious to know that if let's say that each cell in the memory has a size of 12 bits then how many bytes of memory can this processor address?
My understanding is that in most cases a processor can hold up to 32 bits which is 4 bytes and each byte is 8 bits. However, in this case, each byte would be 12 bits and the processor would be able to address 2^26/12 bytes of memory. Is that safe to say?
I'm thinking that the maximum number it can hold would be 2^26 - 1 and can have 2^26 unique memory addresses.
I agree. We usually refer to this as the size of the address space.
As for the next question:
These days, the term byte is generally agreed to means 8 bits, so 12 bits would mean 1.5 bytes. It is a matter of terminology, though, which has varied in the long past.
So, I would say 226 12-bit words is capable of holding/storing 226 * 1.5 bytes, though they are not individually addressable, and would have to be packed & unpacked to access the separate bytes.
The DEC PDP-8 computer was a 12 bit computer and word addressable, so there were multiple schemes for storing characters: two 6 bit characters in a 12 bit word, and also 1 & 1/2 8-bit characters in a 12-bit word, so three 8-bit characters in two 12-bit words.
Similar issues occur when storing packed booleans in a memory, where each boolean takes only a single bit, yet the processor can access a minimum of 8 bits at a time, so must extract a single bit from a larger datum.
I'm reading a book about assembly; Jones and Bartlett Publishers Introduction to 80x86 Assembly
The author give exercises but no answers to it. Obviously before going further, I want
to make sure that I fully understand the chapter concepts.
donc,
What is the 8-hex-digit address of the "last" byte for a PC with 32 MBytes of RAM
This is my solution:
1) convert to bits
32 MBytes = 268435456 bits
2) I subtract 8 bits to remove the last byte
268435448
3) conversion to hexadecimal
FFFFFF8
So I got FFFFFF8
Does this look a good answer?
No. For assembly programming it's very helpful to be able to do simple power-of-2 calculations in your head. 1K is 2^10. So 1M is 2^20. So 32M is 2^25 (because 2^5 = 32). So the address of the last byte is 2^25-1 (because the first byte is at 0). This is 25 bits that are all 1's (because 2^n-1 is always n 1's). In hex, this is six F's (4 bits per F) plus an additional 1, so prepending a zero to get 8 hex digits, you have 01FFFFFF.
There are two things you should think about:
For most computers (all PCs) adresses are given in bytes, not in bits.
Therefore you must calculate: 32 MByte = 33554432 Bytes, minus 1 byte = 01FFFFFF (hex) as "Gene" wrote in his answer.
In reality (if you are interested in) you must also think about the fact that there is a "gap" in the address area (from 000A0000 to 000FFFFF) of real PCs so either not all the RAM is useable or the last address of the RAM comes later. This area is used for the graphics card and the BIOS ROM.
I thinking is : 00007FFF
because: 32MB = 32*1024 = 32768
byte last have address 32767 (7FFF)
On this page, there is an example image of part of memory layout for a program :
What does each line in such an image represent? Does each line represent a single line of physical memory ? Usually physical memory has 32-bit or 64 bit as each line, so in that case, does each line in the image cover several lines of physical memory ?
Thanks.
Each two digit group represents one octet (byte). They are often laid out in groups of 16 octets because it fits well on a printed page or terminal screen. The address of the leftmost octet is in the left column (e.g. 00430020).
This representation is used as a typographic convention and does not necessarily have any relation to the physical structure of memory.
One would hope it was patently obvious, but...
Each line in the above diagram represents 16 bytes (given that the address advances by hex 0x10 with each line and given that there are 16 bytes on each line).
"Usually physical memory has 32-bit or 64 bit as each line" -- Well, no. Physical memory is primarily divided into 8-bit bytes. The computer may have a 32 or 64-bit wide transfer path from memory to the CPU, but the width of that path is irrelevant to understanding diagrams such as the above. (The term "line" inside a computer basically applies only to "cache line", which is a group of bytes from maybe 16 bytes long to possibly 256 bytes long (depending on the design) which are together in a "cache" -- a high-speed "snapshot" of portions of memory. But such cache operates "transparently" so you can ignore its existence for most purposes.)
What you will observe in the above diagram is that the data in a 32-bit address is "little endian" -- the first "next" field is 30 00 43 00, while the location it's pointing to is 00430030. The bytes in memory are reversed from how you or I would "naturally" read them.
So this diagram is simply showing some simple structures in memory and how they address each other.
Well i probably could have asked the professor about this, but i haven't been going to faculty very often in the past few weeks so i'll ask anyone who comes across this.
In MIPS if an the starting address of an array of integers (the address of A[0]) is stored in the register $s3 then the assembler code for storing the 9th element of the array in the temporary register $t0 will be lw $t0 32($s3). So the offset is 32. The explanation for this is that most architectures today reference every byte in memory(i.e. every memory cell) and since an integer is 4 bytes which is the most common size of a "word" the address for the next integer in memory would be the current address + 4 , making address for 9th integer: starting address + 4*8. Nice!
Now i know that for a character encoded in ASCII the number of bits needed is 8 = 1 byte. So what i want to ask is if we have an array of chars will it be the case that the next character's address in the array is: "the current address + 1" since for chat only 1 memory cell is needed and every memory cell has its own address? Or, because the word size in the architecture is 4 bytes, the smallest amount that can be referenced is a word although every memory cell has its own address, making the character take 4 byes despite only needing 1? If the first case if true how would the processor know weather to add 1 to the address of 4? Wouldn't it be needed for an additional instruction being made by the compiler for determining the data type? Also, cause the int took the space referenced by 4 addresses, is the address which the processor uses to load the integer that of the first byte or?
Now i'm on cache memory(by the way i'm learning from Patterson and Hennessy's Computer organization and design) and this thing really bothers me so i would be grateful if someone
would answer. So, thanks!
if we have an array of chars will it be the case that the next character's address in the array is: "the current address + 1 [byte]" ?
Yes.
If [this] is true how would the processor know weather to add 1 to the address of 4? Wouldn't it be needed for an additional instruction being made by the compiler for determining the data type?
There are additional instructions. lw is used for loading words, while lb/lbu is used for loading bytes. But that only affects the size of the data to load. The offsets aren't scaled according to the data size like they are in C. If you use an offset of 3 for an lw it will try to load from the address given by the base register + 3 bytes.
Also, cause the int took the space referenced by 4 addresses, is the address which the processor uses to load the integer that of the first byte or?
Yes. And the layout of the word value in memory depends on the endianness of the CPU. The value 0x12345678 on a little-endian system would be stored as:
-- address -->
78 56 34 12
and on a big-endian system it would be stored as:
-- address -->
12 34 56 78
I am working with the MIPS architecture (not sure if this is relevant since we are dealing with memory).
I am told that A 32-bit integer is in memory at physical address 0x00A0CE48.
I assume that number is 00000000111111110000000011111111.
The system is byte-addressable, what value would be at memory address 0x00A0?
I wasn't sure if the first 8 bits were at address 0x00, next 8 bits at 0x00A0, next 8 bits at 0x00A0CE, and the last 8 bits at 0x00A0CE48? I'm asking because I have to manipulate a value in 0x00A0, but im not sure what's there.
Part of the problem is to 1st assume big endian is used, then little endian.
A 32-bit integer resides in memory at physical address 0x00A0CE48. The bits within the 32-bit word are numbered 0 to 31 from least significant bit to most significant bit. The code below extracts a single bit from this 32 bit pattern and places the bit into $t4.
lui $t0,0x00A0
ori $t0,$t0,0xCE48
lbu $t4,2($t0)
srl $t4,$t4,5
andi $t4,$t4,1
The next question in my assignment is to indicate the number of the bit (0 through 31) within the 32-bit word that is left in $t4 if the memory order used is little-endian or big-endian.
On a big endian system, the most significant byte is stored first. So, assuming the value is 0x12345678, 0x12 will be stored at address 0x00A0CE48, 0x34 will be stored at address 0x00A0CE49, 0x56 will be stored at address 0x00A0CE4A, and 0x78 will be stored at address 0x00A0CE4B.
On the other hand, on a little endian system, the least significant byte will be stored first. So, 0x78 would be stored at 0x00A0CE48, and so on.
Note that if a 32-bit word is stored at address 0x00A0CE48, the next word will be four bytes later, at address 0x00A0CE4C. The arithmetic should be performed on the address as a whole. You cannot consider the bytes making up the address separately when reading from memory.
In the assembly you've posted, lui (which stands for "load upper immediate") will shift the immediate value 16 bits to the left and store it in $t0. After that instruction, the value in $t0 will be 0x00A00000. The next instruction will OR the contents of $t0 with 0xCE48 and store the results in $t0. After that, $t0 will contain your full address, 0x00A0CE48.