I'm trying to write a simple machine learning application in Ada, and also trying to find a good framework to use. My knowledge of one thing is extremely minimal, and of the other is somewhat minimal.
There are several nifty machine learning frameworks out there, and I'd like to leverage one for use with an Ada program, but I guess I'm just...at a loss. Can I use an existing framework written in Python, for instance and wrap (or I guess, bind?) the API calls in Ada? Should I just pass off the scripting capabilities? I'm trying to figure it out.
Case in point: Scikit (sklearn)
https://scikit-learn.org/stable/tutorial/text_analytics/working_with_text_data.html#
This does some neat stuff, and I'd like to be able to leverage this, but with an Ada program. Does anyone have advice from a similar experience?
I am just researching, so I have tried finding information.
http://www.inspirel.com/articles/Ada_Python_Binding.html
https://scikit-learn.org/stable/tutorial/text_analytics/working_with_text_data.html#
The inspirel solution is based on python2.7. If you're using anything from python3.5 onwards a few mods need to be made. On Linux, changing to say python 3.7, you'd just change
--for Default_Switches ("Ada") use ("-lpython2.7");
for Default_Switches ("Ada") use ("-lpython3.7");
but on windows, the libraries aren't dumped in a community lib so gnat doesn't know where to find them. All the packages are kept separately. The -L has to be added to tell the linker where to find the library. Alternatively, you can use for lib_dir. In my case, I did a non-admin install of python, so it looks something like
for Default_Switches ("Ada") use ("-L\Users\StdUser\AppData\Local\Programs\Python\Python37-32\libs", "-lpython37");
Note that on windows, the library is called python37: not python3.7. Use gprbuild instead of gnatmake -p, which has been deprecated. If you do all your mods correctly
gprbuild ada_main.gpr
should give you an executable in obj\ada_main.exe if it builds. If a later version of python is used, some edits need to be made
python_module.py
#print 'Hello from Python module'
print('Hello from Python module')
#print 'Python adding:', a, '+', b
print('Python adding:', a, '+', b)
ada_main.adb
-- Python.Execute_String("print 'Hello from Python!'");
Python.Execute_String("print('Hello from Python!')");
Some routines have been deprecated so the linkage has to change
python.adb
--pragma Import(C, PyInt_AsLong, "PyInt_AsLong");
pragma Import(C, PyInt_AsLong, "PyLong_AsLong");
--pragma Import(C, PyString_FromString, PyString_FromString");
pragma Import(C, PyString_FromString, "PyUnicode_FromString");
Running the build and executable should give
C:\Users\StdUser\My Documents\ada-python>gprbuild ada_main.gpr
Compile
[Ada] ada_main.adb
Bind
[gprbind] ada_main.bexch
[Ada] ada_main.ali
Link
[link] ada_main.adb
C:\Users\StdUser\My Documents\ada-python>obj\ada_main.exe
executing Python directly from Ada:
Hello from Python!
loading external Python module and calling functions from that module:
Hello from Python module!
asking Python to add two integers:
Python adding: 10 + 2
Ada got result from Python: 12
we can try other operations, too:
subtract: 8
multiply: 20
divide : 5
Remember to put the pythonxx.dll somewhere on your path otherwise it won't be able to find the library when it starts executing.
I've been experimenting with PyCharm in conjunction with LO and UNO for some time (win10).
What I don't understand:
Why do I get the error Unresolved reference 'com' from PyCharm when I enter the code in editor, but everything seems to be OK, when I run the script with PyCharm or entered in console?
Example:
import uno
from com.sun.star.awt import Point
p = Point(100, 200)
print(p)
=> (com.sun.star.awt.Point){ X = (long)0x64, Y = (long)0xc8 }
What I would expect would be a relationship between the UNO interfaces com.sun.star.awt and Python so that I can use Intellisense/autocomplete (for example) when entering the code from com.sun.star.awt import Point in PyCharm'.
What I know is that all interfaces are described in the IDL files (SDK). I thought it must be possible to define a so-called stub/mock "package" that enables me to do this. Unfortunately, this request is beyond my capabilities at the moment. The attempt to integrate the idl structure from sdk is only inadequate (path structure only).
Are there any ready-made solutions? (which I doubt - intensively searched all sources)
Do I have to live with it now, or which approach would go in the right direction (I love intellisense)? - Maybe I think too complicated?
I have 2 types of ARDUINO-cards. ATMEGA 2560 and ATMEGA 328P.
In my Delphi7 (XP64 sp2) I have modified the JvHidDeviceController Unit to show the PID/VID's of the abovementioned Cards. That works perfectly. And with the use of the TComPort unit I can communicate with the selected card. No problems here.
And here is the problem:
I connect my AVR MARK II (usb-tiny). System "says" OK.
(When I run the ARUINO program I have no problems communicating with the connected card.)
I run the Delphi program (JVHidDeviceController Unit), the 2560 and 328p PID/VID appear in a LIST-box but NOT the AVR-MARK II.
I Wonder why ? Please help.
After a search on the WWW I discovered, that the UNO (328P) could be turned into a ISP programmer. And by doing so I solve 2 (sub-)problems. I got the code ("bootloader") and the UNO Stills responds to the JVHidDeviceController requests. (Final solution in reach.. ) Kris
I am working on new costume board based on (i. MX 6Solo6DualLite).and I use (TJA1100 100BASE-T1 PHY) for Automotive Ethernet..
please correct me if my questions don't make sense, or I am in the wrong way.
I want to write driver for this device.. and make sure that it works correctly.
1- I can make sure that the driver works properly in the U-boot step, Right? I mean no need to load Linux kernel, so I have just to add source code C driver in U-boot source code and compile it. I want to do this in U-boot step, so I can limit the numbers of files that initialise all peripheriques, and make it simple as possible since that U-boot can behave like (mini-Os)
2-I don't know how to write this driver (exactly..), so I am looking for the driver (source code) that initialise the Ethernet Controller in any other processor , and initialise another typeof ethernet phy, in order to get an idea and write a similar driver source code for I.MX6 and TJA1100,?
after this i think that i could maybe add some very basic file c For simple Protocol like ARP, for test purpose..
3- is this good idea writing driver code by inspiring from another driver code source?
4 - maybe, if you already have a driver for (i. MX 6Solo6DualLite and TJA1100 100BASE-T1 PHY) can you provide to me please... ?
for my second question i tried to extract from U-boot source code the C file that initialise Ethernet Controller in AM335x, and initialise LAN8710A phy,(in beaglebone black) in order to get an idea and write a similar driver source code but i couldn't found it .. i found network C file for protocol .... but that's disturp me i couldn't seperate them from the real C file that initialise ethernet controller and ethernent Phy .
http://www.denx.de/wiki/U-Boot/SourceCode
There is a driver published on the NXP forum:
https://community.nxp.com/thread/460767
It includes both some bare metal code that should be usable with U-Boot and a Linux driver.
I have an example design in system generator for image processing which has one input image and one output image.
I would like to send data through AXI stream interface and export it as an IP core to Vivado IP integrator and develop the design further using DMA and software in SDK.
Firstly is it possible to have AXI stream interface in my design? If yes, how can I implement it? Can anybody help me?
Thanks in advance.
(i have attached image of the example here)
Image_filter
Firstly is it possible to have AXI stream interface in my design?
Yes, it is.
If yes, how can I implement it? Can anybody help me?
I have a similar project develop in Vivado 2015.3: an image filter (created with "High Level Synthesis") and this design block:
The High Level Synthesis code should look like:
#include "top.h"
void hls_sobel(
hls::stream< ap_axiu<8,1,1,1> > &video_in,
hls::stream< ap_axiu<8,1,1,1> > &video_out
)
{
ap_uint<16> Image_w=IMAGE_W_MAX;
ap_uint<16> Image_h=IMAGE_H_MAX;
// Create AXI streaming interfaces for the core
#pragma HLS INTERFACE axis port=video_in bundle=video_in
#pragma HLS INTERFACE axis port=video_out bundle=video_out
// No control interface - auto-start as soon as there's an input frame
#pragma HLS INTERFACE ap_ctrl_none port=return // no handshakes
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> mat_in(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> mat_out(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> inx(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> iny(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> sobelx(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> sobely(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> zerox(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_16SC1> zeroy(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> absx(Image_h, Image_w);
hls::Mat<IMAGE_H_MAX, IMAGE_W_MAX, HLS_8UC1> absy(Image_h, Image_w);
#pragma HLS dataflow
// read input and convert from axi-stream to Mat
hls::AXIvideo2Mat(video_in, mat_in);
// calculate Sobel in X and Y directions
hls::Duplicate(mat_in, inx, iny);
hls::Sobel<1,0,3>(inx, sobelx);
hls::Sobel<0,1,3>(iny, sobely);
// calculate abs of said Sobel
hls::Zero(zerox);
hls::Zero(zeroy);
hls::AbsDiff(sobelx, zerox, absx);
hls::AbsDiff(sobely, zeroy, absy);
// add both abs
hls::AddWeighted(absx, 1, absy, 1, 0, mat_out);
// write output
hls::Mat2AXIvideo(mat_out, video_out);
}
As you can note, a DMA is used. For the Video-Image application, I recommend using a Video-DMA (VDMA) to send all the pixel information via streaming-interface. After, in the SDK, it is easy to manage the transfer using the function in the Board Support Package (BSP).
Also, you can note that in the code above is explicitly specified hls::stream< ap_axiu<8,1,1,1> > &video_in,! In this way, I am creating a streaming interface.
Here you can find a tutorial about HLS image processing filter. In the last page, there are useful links. Follow them to realize the same system of the example.
I hope this can help
I am currently working on a very similar project, (I am not using System Generator though), so I bet I could give you some pointers. As far as I remember SysGen can produce some VHDL or Verilog code of your design. So:
After you get the HDL code of your design, pack it as a new IP in Vivado. There are plenty of tutorials on how to do this, it should be easy with a little search. You should wisely choose the interfaces you want to implement. You're going to definitely need an AXI Stream Slave interface for accepting the incoming data and an AXI Stream Master interface to transmit the results.
After you package your IP, you can begin building your system block-by-block (there are also some good tutorials on this, see end of answer). You will need to use the AXI DMA IP (or the Video DMA, depending on your needs) and you'll have to configure it properly, like choosing register-mode or scatter-gather, channels, etc.
Be extremely careful to generate the proper AXI synchronization signals correctly, as they can totally ruin your design (and nerves). It's easy but it requires some study of the AXI documentation provided by Xilinx (ARM's docs are too complicated for my taste).
Finally, you will definitely find very useful information on the following resources:
Xilinx Forum
FPGAdeveloper's example
another AXI-stream based design example
FPGA note wiki
AXI DMA Product Guide
Channel of Dr. Sadri of TU Kaiserslautern, really helpful to deeply understand AXI design concepts
Good luck!
PS: Simulators are your friends! Never try implementing your freshly written code directly onto the system design. Modelsim can save you significant time and effort which would otherwise be spent on pointless debugging.
If I understand correctly, you want to know how to create an AXI Stream interface inside your system generator design.
Yes it is possible to do it. You should have atleast two inputs in your design with names, for example, image_tdata and image_tvalid (gateway in). When you generate IP core, sysgen will recoginize this as an AXI STREAM. The format is important. It must be "$customname_tdata" and "$customname_tvalid". You can add other inputs as well to add to the AXI STREAM such as "$customname_tlast", "$customname_tready".